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Searched refs:dev_priv (Results 1 – 25 of 141) sorted by relevance

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/linux/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_drv.c346 static void vmw_print_sm_type(struct vmw_private *dev_priv) in vmw_print_sm_type() argument
357 drm_info(&dev_priv->drm, "Available shader model: %s.\n", in vmw_print_sm_type()
358 names[dev_priv->sm_type]); in vmw_print_sm_type()
374 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) in vmw_dummy_query_bo_create() argument
395 ret = vmw_bo_create(dev_priv, &bo_params, &vbo); in vmw_dummy_query_bo_create()
414 dev_priv->dummy_query_bo = vbo; in vmw_dummy_query_bo_create()
419 static int vmw_device_init(struct vmw_private *dev_priv) in vmw_device_init() argument
423 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
424 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); in vmw_device_init()
425 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); in vmw_device_init()
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H A Dvmwgfx_irq.c57 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_thread_fn() local
61 dev_priv->irqthread_pending)) { in vmw_thread_fn()
62 vmw_fences_update(dev_priv->fman); in vmw_thread_fn()
63 wake_up_all(&dev_priv->fence_queue); in vmw_thread_fn()
68 dev_priv->irqthread_pending)) { in vmw_thread_fn()
69 vmw_cmdbuf_irqthread(dev_priv->cman); in vmw_thread_fn()
90 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_irq_handler() local
94 status = vmw_irq_status_read(dev_priv); in vmw_irq_handler()
95 masked_status = status & READ_ONCE(dev_priv->irq_mask); in vmw_irq_handler()
98 vmw_irq_status_write(dev_priv, status); in vmw_irq_handler()
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H A Dvmwgfx_cmd.c36 bool vmw_supports_3d(struct vmw_private *dev_priv) in vmw_supports_3d() argument
39 const struct vmw_fifo_state *fifo = dev_priv->fifo; in vmw_supports_3d()
41 if (!(dev_priv->capabilities & SVGA_CAP_3D)) in vmw_supports_3d()
44 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { in vmw_supports_3d()
47 if (!dev_priv->has_mob) in vmw_supports_3d()
50 result = vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_3D); in vmw_supports_3d()
55 if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) in vmw_supports_3d()
58 BUG_ON(vmw_is_svga_v3(dev_priv)); in vmw_supports_3d()
60 fifo_min = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_MIN); in vmw_supports_3d()
64 hwversion = vmw_fifo_mem_read(dev_priv, in vmw_supports_3d()
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H A Dvmwgfx_context.c121 static void vmw_context_cotables_unref(struct vmw_private *dev_priv, in vmw_context_cotables_unref() argument
126 u32 cotable_max = has_sm5_context(dev_priv) ? in vmw_context_cotables_unref()
144 struct vmw_private *dev_priv = res->dev_priv; in vmw_hw_context_destroy() local
153 mutex_lock(&dev_priv->cmdbuf_mutex); in vmw_hw_context_destroy()
155 mutex_lock(&dev_priv->binding_mutex); in vmw_hw_context_destroy()
158 mutex_unlock(&dev_priv->binding_mutex); in vmw_hw_context_destroy()
159 if (dev_priv->pinned_bo != NULL && in vmw_hw_context_destroy()
160 !dev_priv->query_cid_valid) in vmw_hw_context_destroy()
161 __vmw_execbuf_release_pinned_bo(dev_priv, NULL); in vmw_hw_context_destroy()
162 mutex_unlock(&dev_priv->cmdbuf_mutex); in vmw_hw_context_destroy()
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H A Dvmwgfx_overlay.c88 static int vmw_overlay_send_put(struct vmw_private *dev_priv, in vmw_overlay_send_put() argument
95 bool have_so = (dev_priv->active_display_unit != vmw_du_legacy); in vmw_overlay_send_put()
119 cmds = VMW_CMD_RESERVE(dev_priv, fifo_size); in vmw_overlay_send_put()
166 vmw_cmd_commit(dev_priv, fifo_size); in vmw_overlay_send_put()
177 static int vmw_overlay_send_stop(struct vmw_private *dev_priv, in vmw_overlay_send_stop() argument
189 cmds = VMW_CMD_RESERVE(dev_priv, sizeof(*cmds)); in vmw_overlay_send_stop()
193 ret = vmw_fallback_wait(dev_priv, false, true, 0, in vmw_overlay_send_stop()
208 vmw_cmd_commit(dev_priv, sizeof(*cmds)); in vmw_overlay_send_stop()
219 static int vmw_overlay_move_buffer(struct vmw_private *dev_priv, in vmw_overlay_move_buffer() argument
224 return vmw_bo_unpin(dev_priv, buf, inter); in vmw_overlay_move_buffer()
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H A Dvmwgfx_ldu.c80 static int vmw_ldu_commit_list(struct vmw_private *dev_priv) in vmw_ldu_commit_list() argument
82 struct vmw_legacy_display *lds = dev_priv->ldu_priv; in vmw_ldu_commit_list()
91 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)) { in vmw_ldu_commit_list()
103 return vmw_kms_write_svga(dev_priv, w, h, fb->pitches[0], in vmw_ldu_commit_list()
112 vmw_kms_write_svga(dev_priv, fb->width, fb->height, fb->pitches[0], in vmw_ldu_commit_list()
117 vmw_write(dev_priv, SVGA_REG_NUM_GUEST_DISPLAYS, in vmw_ldu_commit_list()
124 vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, i); in vmw_ldu_commit_list()
125 vmw_write(dev_priv, SVGA_REG_DISPLAY_IS_PRIMARY, !i); in vmw_ldu_commit_list()
126 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_X, crtc->x); in vmw_ldu_commit_list()
127 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, crtc->y); in vmw_ldu_commit_list()
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H A Dvmwgfx_drv.h137 struct vmw_private *dev_priv; member
337 struct vmw_private *dev_priv; member
659 static inline void vmw_write(struct vmw_private *dev_priv, in vmw_write() argument
662 if (vmw_is_svga_v3(dev_priv)) { in vmw_write()
663 iowrite32(value, dev_priv->rmmio + offset); in vmw_write()
665 spin_lock(&dev_priv->hw_lock); in vmw_write()
666 outl(offset, dev_priv->io_start + SVGA_INDEX_PORT); in vmw_write()
667 outl(value, dev_priv->io_start + SVGA_VALUE_PORT); in vmw_write()
668 spin_unlock(&dev_priv->hw_lock); in vmw_write()
672 static inline uint32_t vmw_read(struct vmw_private *dev_priv, in vmw_read() argument
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H A Dvmwgfx_execbuf.c129 static int vmw_resource_context_res_add(struct vmw_private *dev_priv,
132 static int vmw_translate_mob_ptr(struct vmw_private *dev_priv,
196 static int vmw_cmd_ctx_first_setup(struct vmw_private *dev_priv, in vmw_cmd_ctx_first_setup() argument
203 ret = vmw_resource_context_res_add(dev_priv, sw_context, res); in vmw_cmd_ctx_first_setup()
208 sw_context->staged_bindings = vmw_binding_state_alloc(dev_priv); in vmw_cmd_ctx_first_setup()
217 node->staged = vmw_binding_state_alloc(dev_priv); in vmw_cmd_ctx_first_setup()
250 static unsigned int vmw_execbuf_res_size(struct vmw_private *dev_priv, in vmw_execbuf_res_size() argument
254 (res_type == vmw_res_context && dev_priv->has_mob)) ? in vmw_execbuf_res_size()
297 struct vmw_private *dev_priv = res->dev_priv; in vmw_execbuf_res_val_add() local
320 priv_size = vmw_execbuf_res_size(dev_priv, res_type); in vmw_execbuf_res_val_add()
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H A Dvmwgfx_resource.c104 struct vmw_private *dev_priv = res->dev_priv; in vmw_resource_release_id() local
105 struct idr *idr = &dev_priv->res_idr[res->func->res_type]; in vmw_resource_release_id()
107 spin_lock(&dev_priv->resource_lock); in vmw_resource_release_id()
111 spin_unlock(&dev_priv->resource_lock); in vmw_resource_release_id()
118 struct vmw_private *dev_priv = res->dev_priv; in vmw_resource_release() local
121 struct idr *idr = &dev_priv->res_idr[res->func->res_type]; in vmw_resource_release()
123 spin_lock(&dev_priv->resource_lock); in vmw_resource_release()
125 spin_unlock(&dev_priv->resource_lock); in vmw_resource_release()
150 mutex_lock(&dev_priv->binding_mutex); in vmw_resource_release()
152 mutex_unlock(&dev_priv->binding_mutex); in vmw_resource_release()
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H A Dvmwgfx_ioctl.c39 struct vmw_private *dev_priv = vmw_priv(dev); in vmw_getparam_ioctl() local
46 param->value = vmw_overlay_num_overlays(dev_priv); in vmw_getparam_ioctl()
49 param->value = vmw_overlay_num_free_overlays(dev_priv); in vmw_getparam_ioctl()
52 param->value = vmw_supports_3d(dev_priv) ? 1 : 0; in vmw_getparam_ioctl()
55 param->value = dev_priv->capabilities; in vmw_getparam_ioctl()
58 param->value = dev_priv->capabilities2; in vmw_getparam_ioctl()
61 param->value = vmw_fifo_caps(dev_priv); in vmw_getparam_ioctl()
64 param->value = dev_priv->max_primary_mem; in vmw_getparam_ioctl()
68 if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS)) in vmw_getparam_ioctl()
72 dev_priv, in vmw_getparam_ioctl()
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H A Dvmwgfx_streamoutput.c93 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_streamoutput_unscrub() local
102 cmd = VMW_CMD_CTX_RESERVE(dev_priv, sizeof(*cmd), so->ctx->id); in vmw_dx_streamoutput_unscrub()
112 vmw_cmd_commit(dev_priv, sizeof(*cmd)); in vmw_dx_streamoutput_unscrub()
121 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_streamoutput_create() local
128 mutex_lock(&dev_priv->binding_mutex); in vmw_dx_streamoutput_create()
130 mutex_unlock(&dev_priv->binding_mutex); in vmw_dx_streamoutput_create()
141 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_streamoutput_bind() local
148 mutex_lock(&dev_priv->binding_mutex); in vmw_dx_streamoutput_bind()
150 mutex_unlock(&dev_priv->binding_mutex); in vmw_dx_streamoutput_bind()
163 struct vmw_private *dev_priv = res->dev_priv; in vmw_dx_streamoutput_scrub() local
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H A Dvmwgfx_shader.c157 static int vmw_gb_shader_init(struct vmw_private *dev_priv, in vmw_gb_shader_init() argument
170 ret = vmw_resource_init(dev_priv, res, true, res_free, in vmw_gb_shader_init()
201 struct vmw_private *dev_priv = res->dev_priv; in vmw_gb_shader_create() local
223 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd)); in vmw_gb_shader_create()
234 vmw_cmd_commit(dev_priv, sizeof(*cmd)); in vmw_gb_shader_create()
235 vmw_fifo_resource_inc(dev_priv); in vmw_gb_shader_create()
248 struct vmw_private *dev_priv = res->dev_priv; in vmw_gb_shader_bind() local
257 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd)); in vmw_gb_shader_bind()
267 vmw_cmd_commit(dev_priv, sizeof(*cmd)); in vmw_gb_shader_bind()
276 struct vmw_private *dev_priv = res->dev_priv; in vmw_gb_shader_unbind() local
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H A Dvmwgfx_kms.c31 struct vmw_private *dev_priv = vmw_priv(du->primary.dev); in vmw_du_cleanup() local
35 if (vmw_cmd_supported(dev_priv)) in vmw_du_cleanup()
458 int vmw_kms_readback(struct vmw_private *dev_priv, in vmw_kms_readback() argument
465 switch (dev_priv->active_display_unit) { in vmw_kms_readback()
467 return vmw_kms_sou_readback(dev_priv, file_priv, vfb, in vmw_kms_readback()
471 return vmw_kms_stdu_readback(dev_priv, file_priv, vfb, in vmw_kms_readback()
500 static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv, in vmw_kms_new_framebuffer_surface() argument
508 struct drm_device *dev = &dev_priv->drm; in vmw_kms_new_framebuffer_surface()
514 if (dev_priv->active_display_unit == vmw_du_legacy) in vmw_kms_new_framebuffer_surface()
523 if (!drm_any_plane_has_format(&dev_priv->drm, in vmw_kms_new_framebuffer_surface()
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/linux/drivers/gpu/drm/gma500/
H A Dpsb_drv.c104 static void psb_spank(struct drm_psb_private *dev_priv) in psb_spank() argument
125 PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); in psb_spank()
130 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_do_init() local
131 struct psb_gtt *pg = &dev_priv->gtt; in psb_do_init()
144 dev_priv->gatt_free_offset = pg->mmu_gatt_start + in psb_do_init()
147 spin_lock_init(&dev_priv->irqmask_lock); in psb_do_init()
158 psb_spank(dev_priv); in psb_do_init()
169 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_driver_unload() local
178 if (dev_priv->ops->chip_teardown) in psb_driver_unload()
179 dev_priv->ops->chip_teardown(dev); in psb_driver_unload()
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H A Dintel_bios.c47 parse_edp(struct drm_psb_private *dev_priv, struct bdb_header *bdb) in parse_edp() argument
56 dev_priv->edp.bpp = 18; in parse_edp()
58 if (dev_priv->edp.support) { in parse_edp()
60 dev_priv->edp.bpp); in parse_edp()
65 panel_type = dev_priv->panel_type; in parse_edp()
68 dev_priv->edp.bpp = 18; in parse_edp()
71 dev_priv->edp.bpp = 24; in parse_edp()
74 dev_priv->edp.bpp = 30; in parse_edp()
82 dev_priv->edp.pps = *edp_pps; in parse_edp()
85 dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, in parse_edp()
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H A Dpsb_irq.c47 void gma_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) in gma_enable_pipestat() argument
49 if ((dev_priv->pipestat[pipe] & mask) != mask) { in gma_enable_pipestat()
51 dev_priv->pipestat[pipe] |= mask; in gma_enable_pipestat()
53 if (gma_power_begin(&dev_priv->dev, false)) { in gma_enable_pipestat()
58 gma_power_end(&dev_priv->dev); in gma_enable_pipestat()
63 void gma_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask) in gma_disable_pipestat() argument
65 if ((dev_priv->pipestat[pipe] & mask) != 0) { in gma_disable_pipestat()
67 dev_priv->pipestat[pipe] &= ~mask; in gma_disable_pipestat()
68 if (gma_power_begin(&dev_priv->dev, false)) { in gma_disable_pipestat()
73 gma_power_end(&dev_priv->dev); in gma_disable_pipestat()
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H A Dbacklight.c24 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_backlight_enable() local
26 dev_priv->backlight_enabled = true; in gma_backlight_enable()
27 dev_priv->ops->backlight_set(dev, dev_priv->backlight_level); in gma_backlight_enable()
32 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_backlight_disable() local
34 dev_priv->backlight_enabled = false; in gma_backlight_disable()
35 dev_priv->ops->backlight_set(dev, 0); in gma_backlight_disable()
40 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_backlight_set() local
42 dev_priv->backlight_level = v; in gma_backlight_set()
43 if (dev_priv->backlight_enabled) in gma_backlight_set()
44 dev_priv->ops->backlight_set(dev, v); in gma_backlight_set()
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H A Dmid_bios.c22 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in mid_get_fuse_settings() local
49 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE; in mid_get_fuse_settings()
52 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display"); in mid_get_fuse_settings()
55 if (dev_priv->iLVDS_enable) { in mid_get_fuse_settings()
56 dev_priv->is_lvds_on = true; in mid_get_fuse_settings()
57 dev_priv->is_mipi_on = false; in mid_get_fuse_settings()
59 dev_priv->is_mipi_on = true; in mid_get_fuse_settings()
60 dev_priv->is_lvds_on = false; in mid_get_fuse_settings()
63 dev_priv->video_device_fuse = fuse_value; in mid_get_fuse_settings()
71 dev_priv->fuse_reg_value = fuse_value; in mid_get_fuse_settings()
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H A Dpower.c48 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_power_init() local
51 dev_priv->apm_base = dev_priv->apm_reg & 0xffff; in gma_power_init()
52 dev_priv->ospm_base &= 0xffff; in gma_power_init()
54 if (dev_priv->ops->init_pm) in gma_power_init()
55 dev_priv->ops->init_pm(dev); in gma_power_init()
70 dev_priv->pm_initialized = true; in gma_power_init()
81 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_power_uninit() local
83 if (!dev_priv->pm_initialized) in gma_power_uninit()
97 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_suspend_display() local
99 dev_priv->ops->save_regs(dev); in gma_suspend_display()
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H A Dintel_gmbus.c57 #define GMBUS_REG_READ(reg) ioread32(dev_priv->gmbus_reg + (reg))
58 #define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg))
73 struct drm_psb_private *dev_priv; member
80 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in gma_intel_i2c_reset() local
84 static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable) in intel_i2c_quirk_set() argument
107 struct drm_psb_private *dev_priv = gpio->dev_priv; in get_reserved() local
121 struct drm_psb_private *dev_priv = gpio->dev_priv; in get_clock() local
131 struct drm_psb_private *dev_priv = gpio->dev_priv; in get_data() local
141 struct drm_psb_private *dev_priv = gpio->dev_priv; in set_clock() local
158 struct drm_psb_private *dev_priv = gpio->dev_priv; in set_data() local
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H A Dgtt.c128 static int psb_gtt_enable(struct drm_psb_private *dev_priv) in psb_gtt_enable() argument
130 struct drm_device *dev = &dev_priv->dev; in psb_gtt_enable()
134 ret = pci_read_config_word(pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl); in psb_gtt_enable()
137 ret = pci_write_config_word(pdev, PSB_GMCH_CTRL, dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED); in psb_gtt_enable()
141 dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL); in psb_gtt_enable()
142 PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL); in psb_gtt_enable()
149 static void psb_gtt_disable(struct drm_psb_private *dev_priv) in psb_gtt_disable() argument
151 struct drm_device *dev = &dev_priv->dev; in psb_gtt_disable()
154 pci_write_config_word(pdev, PSB_GMCH_CTRL, dev_priv->gmch_ctrl); in psb_gtt_disable()
155 PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL); in psb_gtt_disable()
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H A Dgem.c33 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_gem_pin() local
34 u32 gpu_base = dev_priv->gtt.gatt_start; in psb_gem_pin()
56 psb_gtt_insert_pages(dev_priv, &pobj->resource, pages); in psb_gem_pin()
57 psb_mmu_insert_pages(psb_mmu_get_default_pd(dev_priv->mmu), pages, in psb_gem_pin()
78 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_gem_unpin() local
79 u32 gpu_base = dev_priv->gtt.gatt_start; in psb_gem_unpin()
96 psb_mmu_remove_pages(psb_mmu_get_default_pd(dev_priv->mmu), in psb_gem_unpin()
98 psb_gtt_remove_pages(dev_priv, &pobj->resource); in psb_gem_unpin()
142 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); in psb_gem_create() local
156 ret = psb_gtt_allocate_resource(dev_priv, &pobj->resource, name, size, align, stolen, in psb_gem_create()
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/linux/drivers/gpu/drm/i915/display/
H A Di9xx_plane_regs.h12 #define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) argument
15 #define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) argument
49 #define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) argument
52 #define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) argument
55 #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) argument
58 #define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) argument
65 #define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) argument
72 #define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) argument
76 #define DSPTILEOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) argument
83 #define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) argument
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H A Dintel_pipe_crc_regs.h12 #define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A) argument
63 #define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A) argument
67 #define PIPE_CRC_EXP_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A) argument
71 #define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I9… argument
75 #define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X) argument
79 #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A) argument
82 #define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A) argument
85 #define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A) argument
88 #define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_… argument
91 #define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A… argument
/linux/drivers/gpu/drm/i915/
H A Di915_vgpu.c64 void intel_vgpu_detect(struct drm_i915_private *dev_priv) in intel_vgpu_detect() argument
66 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in intel_vgpu_detect()
79 if (GRAPHICS_VER(dev_priv) < 6) in intel_vgpu_detect()
84 drm_err(&dev_priv->drm, in intel_vgpu_detect()
95 drm_info(&dev_priv->drm, "VGT interface version mismatch!\n"); in intel_vgpu_detect()
99 dev_priv->vgpu.caps = readl(shared_area + vgtif_offset(vgt_caps)); in intel_vgpu_detect()
101 dev_priv->vgpu.active = true; in intel_vgpu_detect()
102 mutex_init(&dev_priv->vgpu.lock); in intel_vgpu_detect()
103 drm_info(&dev_priv->drm, "Virtual GPU for Intel GVT-g detected.\n"); in intel_vgpu_detect()
119 bool intel_vgpu_active(struct drm_i915_private *dev_priv) in intel_vgpu_active() argument
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