Lines Matching refs:dev_priv
346 static void vmw_print_sm_type(struct vmw_private *dev_priv)
357 drm_info(&dev_priv->drm, "Available shader model: %s.\n",
358 names[dev_priv->sm_type]);
364 * @dev_priv: A device private structure.
374 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
395 ret = vmw_bo_create(dev_priv, &bo_params, &vbo);
414 dev_priv->dummy_query_bo = vbo;
419 static int vmw_device_init(struct vmw_private *dev_priv)
423 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
424 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
425 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
427 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE |
430 uses_fb_traces = !vmw_cmd_supported(dev_priv) &&
431 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0;
433 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces);
434 dev_priv->fifo = vmw_fifo_create(dev_priv);
435 if (IS_ERR(dev_priv->fifo)) {
436 int err = PTR_ERR(dev_priv->fifo);
437 dev_priv->fifo = NULL;
439 } else if (!dev_priv->fifo) {
440 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
443 u32 seqno = vmw_fence_read(dev_priv);
445 atomic_set(&dev_priv->last_read_seqno, seqno);
446 atomic_set(&dev_priv->marker_seq, seqno);
474 * @dev_priv: Pointer to device private.
481 static int vmw_request_device_late(struct vmw_private *dev_priv)
485 if (dev_priv->has_mob) {
486 ret = vmw_otables_setup(dev_priv);
494 if (dev_priv->cman) {
495 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096);
497 struct vmw_cmdbuf_man *man = dev_priv->cman;
499 dev_priv->cman = NULL;
507 static int vmw_request_device(struct vmw_private *dev_priv)
511 ret = vmw_device_init(dev_priv);
516 vmw_fence_fifo_up(dev_priv->fman);
517 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
518 if (IS_ERR(dev_priv->cman)) {
519 dev_priv->cman = NULL;
520 dev_priv->sm_type = VMW_SM_LEGACY;
523 ret = vmw_request_device_late(dev_priv);
527 ret = vmw_dummy_query_bo_create(dev_priv);
534 if (dev_priv->cman)
535 vmw_cmdbuf_remove_pool(dev_priv->cman);
536 if (dev_priv->has_mob) {
539 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
540 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
541 vmw_otables_takedown(dev_priv);
543 if (dev_priv->cman)
544 vmw_cmdbuf_man_destroy(dev_priv->cman);
546 vmw_fence_fifo_down(dev_priv->fman);
547 vmw_device_fini(dev_priv);
554 * @dev_priv: Pointer to device private struct.
559 static void vmw_release_device_early(struct vmw_private *dev_priv)
566 BUG_ON(dev_priv->pinned_bo != NULL);
568 vmw_bo_unreference(&dev_priv->dummy_query_bo);
569 if (dev_priv->cman)
570 vmw_cmdbuf_remove_pool(dev_priv->cman);
572 if (dev_priv->has_mob) {
575 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
576 ttm_resource_manager_evict_all(&dev_priv->bdev, man);
577 vmw_otables_takedown(dev_priv);
584 * @dev_priv: Pointer to device private struct.
589 static void vmw_release_device_late(struct vmw_private *dev_priv)
591 vmw_fence_fifo_down(dev_priv->fman);
592 if (dev_priv->cman)
593 vmw_cmdbuf_man_destroy(dev_priv->cman);
595 vmw_device_fini(dev_priv);
607 static void vmw_get_initial_size(struct vmw_private *dev_priv)
612 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
613 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
618 if (width > dev_priv->fb_max_width ||
619 height > dev_priv->fb_max_height) {
629 dev_priv->initial_width = width;
630 dev_priv->initial_height = height;
637 * @dev_priv: Pointer to a struct vmw_private
645 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
658 dev_priv->map_mode = vmw_dma_alloc_coherent;
660 dev_priv->map_mode = vmw_dma_map_bind;
662 dev_priv->map_mode = vmw_dma_map_populate;
664 drm_info(&dev_priv->drm,
665 "DMA map mode: %s\n", names[dev_priv->map_mode]);
672 * @dev_priv: Pointer to struct drm-device
677 static int vmw_dma_masks(struct vmw_private *dev_priv)
679 struct drm_device *dev = &dev_priv->drm;
684 drm_info(&dev_priv->drm,
692 static int vmw_vram_manager_init(struct vmw_private *dev_priv)
695 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,
696 dev_priv->vram_size >> PAGE_SHIFT);
697 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false);
701 static void vmw_vram_manager_fini(struct vmw_private *dev_priv)
703 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM);
817 static void vmw_sw_context_init(struct vmw_private *dev_priv)
819 struct vmw_sw_context *sw_context = &dev_priv->ctx;
824 static void vmw_sw_context_fini(struct vmw_private *dev_priv)
826 struct vmw_sw_context *sw_context = &dev_priv->ctx;
833 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
839 vmw_sw_context_init(dev_priv);
841 mutex_init(&dev_priv->cmdbuf_mutex);
842 mutex_init(&dev_priv->binding_mutex);
843 spin_lock_init(&dev_priv->resource_lock);
844 spin_lock_init(&dev_priv->hw_lock);
845 spin_lock_init(&dev_priv->waiter_lock);
846 spin_lock_init(&dev_priv->cursor_lock);
848 ret = vmw_setup_pci_resources(dev_priv, pci_id);
851 ret = vmw_detect_version(dev_priv);
857 idr_init_base(&dev_priv->res_idr[i], 1);
858 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
861 init_waitqueue_head(&dev_priv->fence_queue);
862 init_waitqueue_head(&dev_priv->fifo_queue);
863 dev_priv->fence_queue_waiters = 0;
864 dev_priv->fifo_queue_waiters = 0;
866 dev_priv->used_memory_size = 0;
868 dev_priv->assume_16bpp = !!vmw_assume_16bpp;
870 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
871 vmw_print_bitmap(&dev_priv->drm, "Capabilities",
872 dev_priv->capabilities,
874 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
875 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
876 vmw_print_bitmap(&dev_priv->drm, "Capabilities2",
877 dev_priv->capabilities2,
881 if (!vmwgfx_supported(dev_priv)) {
883 drm_err_once(&dev_priv->drm,
885 drm_err_once(&dev_priv->drm,
887 drm_err_once(&dev_priv->drm,
891 vmw_vkms_init(dev_priv);
893 ret = vmw_dma_select_mode(dev_priv);
895 drm_info(&dev_priv->drm,
898 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
899 drm_info(&dev_priv->drm,
903 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
904 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
905 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
906 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
908 vmw_get_initial_size(dev_priv);
910 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
911 dev_priv->max_gmr_ids =
912 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
913 dev_priv->max_gmr_pages =
914 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
915 dev_priv->memory_size =
916 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
917 dev_priv->memory_size -= dev_priv->vram_size;
923 dev_priv->memory_size = 512*1024*1024;
925 dev_priv->max_mob_pages = 0;
926 dev_priv->max_mob_size = 0;
927 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
930 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)
931 mem_size = vmw_read(dev_priv,
935 vmw_read(dev_priv,
938 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
939 dev_priv->max_primary_mem =
940 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
941 dev_priv->max_mob_size =
942 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
943 dev_priv->stdu_max_width =
944 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
945 dev_priv->stdu_max_height =
946 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
948 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
950 dev_priv->texture_max_width = vmw_read(dev_priv,
952 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
954 dev_priv->texture_max_height = vmw_read(dev_priv,
957 dev_priv->texture_max_width = 8192;
958 dev_priv->texture_max_height = 8192;
959 dev_priv->max_primary_mem = dev_priv->vram_size;
961 drm_info(&dev_priv->drm,
963 (u64)dev_priv->vram_size / 1024,
964 (u64)dev_priv->fifo_mem_size / 1024,
965 dev_priv->memory_size / 1024);
967 drm_info(&dev_priv->drm,
969 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages);
971 ret = vmw_dma_masks(dev_priv);
975 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);
977 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
978 drm_info(&dev_priv->drm,
980 (unsigned)dev_priv->max_gmr_ids);
981 drm_info(&dev_priv->drm,
983 (unsigned)dev_priv->max_gmr_pages);
985 drm_info(&dev_priv->drm,
987 (uint64_t)dev_priv->max_primary_mem / 1024);
990 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
991 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
992 !vmw_fifo_have_pitchlock(dev_priv)) {
998 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops);
1000 if (unlikely(dev_priv->tdev == NULL)) {
1001 drm_err(&dev_priv->drm,
1007 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
1008 ret = vmw_irq_install(dev_priv);
1010 drm_err(&dev_priv->drm,
1016 dev_priv->fman = vmw_fence_manager_init(dev_priv);
1017 if (unlikely(dev_priv->fman == NULL)) {
1022 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver,
1023 dev_priv->drm.dev,
1024 dev_priv->drm.anon_inode->i_mapping,
1025 dev_priv->drm.vma_offset_manager,
1026 dev_priv->map_mode == vmw_dma_alloc_coherent,
1029 drm_err(&dev_priv->drm,
1039 ret = vmw_vram_manager_init(dev_priv);
1041 drm_err(&dev_priv->drm,
1046 ret = vmw_devcaps_create(dev_priv);
1048 drm_err(&dev_priv->drm,
1058 dev_priv->has_gmr = true;
1060 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
1062 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {
1063 drm_info(&dev_priv->drm,
1066 dev_priv->has_gmr = false;
1069 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {
1070 dev_priv->has_mob = true;
1072 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {
1073 drm_info(&dev_priv->drm,
1076 dev_priv->has_mob = false;
1078 if (vmw_sys_man_init(dev_priv) != 0) {
1079 drm_info(&dev_priv->drm,
1082 dev_priv->has_mob = false;
1086 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
1087 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT))
1088 dev_priv->sm_type = VMW_SM_4;
1092 if (has_sm4_context(dev_priv) &&
1093 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
1094 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41))
1095 dev_priv->sm_type = VMW_SM_4_1;
1096 if (has_sm4_1_context(dev_priv) &&
1097 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) {
1098 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) {
1099 dev_priv->sm_type = VMW_SM_5;
1100 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43))
1101 dev_priv->sm_type = VMW_SM_5_1X;
1106 ret = vmw_kms_init(dev_priv);
1109 vmw_overlay_init(dev_priv);
1111 ret = vmw_request_device(dev_priv);
1115 vmw_print_sm_type(dev_priv);
1119 vmw_write_driver_id(dev_priv);
1121 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
1122 register_pm_notifier(&dev_priv->pm_nb);
1127 vmw_overlay_close(dev_priv);
1128 vmw_kms_close(dev_priv);
1130 if (dev_priv->has_mob) {
1131 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1132 vmw_sys_man_fini(dev_priv);
1134 if (dev_priv->has_gmr)
1135 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1136 vmw_devcaps_destroy(dev_priv);
1137 vmw_vram_manager_fini(dev_priv);
1139 ttm_device_fini(&dev_priv->bdev);
1141 vmw_fence_manager_takedown(dev_priv->fman);
1143 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1144 vmw_irq_uninstall(&dev_priv->drm);
1146 ttm_object_device_release(&dev_priv->tdev);
1149 idr_destroy(&dev_priv->res_idr[i]);
1151 if (dev_priv->ctx.staged_bindings)
1152 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1159 struct vmw_private *dev_priv = vmw_priv(dev);
1162 unregister_pm_notifier(&dev_priv->pm_nb);
1164 vmw_sw_context_fini(dev_priv);
1165 vmw_fifo_resource_dec(dev_priv);
1167 vmw_svga_disable(dev_priv);
1169 vmw_vkms_cleanup(dev_priv);
1170 vmw_kms_close(dev_priv);
1171 vmw_overlay_close(dev_priv);
1173 if (dev_priv->has_gmr)
1174 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1176 vmw_release_device_early(dev_priv);
1177 if (dev_priv->has_mob) {
1178 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1179 vmw_sys_man_fini(dev_priv);
1181 vmw_devcaps_destroy(dev_priv);
1182 vmw_vram_manager_fini(dev_priv);
1183 ttm_device_fini(&dev_priv->bdev);
1184 vmw_release_device_late(dev_priv);
1185 vmw_fence_manager_takedown(dev_priv->fman);
1186 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1187 vmw_irq_uninstall(&dev_priv->drm);
1189 ttm_object_device_release(&dev_priv->tdev);
1192 idr_destroy(&dev_priv->res_idr[i]);
1194 vmw_mksstat_remove_all(dev_priv);
1208 struct vmw_private *dev_priv = vmw_priv(dev);
1216 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev);
1322 * @dev_priv: Pointer to device private struct.
1325 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1327 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1330 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE);
1338 * @dev_priv: Pointer to device private struct.
1340 void vmw_svga_enable(struct vmw_private *dev_priv)
1342 __vmw_svga_enable(dev_priv);
1348 * @dev_priv: Pointer to device private struct.
1352 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1354 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1358 vmw_write(dev_priv, SVGA_REG_ENABLE,
1368 * @dev_priv: Pointer to device private struct.
1371 void vmw_svga_disable(struct vmw_private *dev_priv)
1373 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1386 vmw_kms_lost_device(&dev_priv->drm);
1388 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man))
1391 vmw_write(dev_priv, SVGA_REG_ENABLE,
1428 struct vmw_private *dev_priv =
1441 dev_priv->suspend_locked = true;
1445 if (READ_ONCE(dev_priv->suspend_locked)) {
1446 dev_priv->suspend_locked = false;
1458 struct vmw_private *dev_priv = vmw_priv(dev);
1460 if (dev_priv->refuse_hibernation)
1497 struct vmw_private *dev_priv = vmw_priv(dev);
1507 ret = vmw_kms_suspend(&dev_priv->drm);
1513 vmw_execbuf_release_pinned_bo(dev_priv);
1514 vmw_resource_evict_all(dev_priv);
1515 vmw_release_device_early(dev_priv);
1516 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0);
1517 vmw_fifo_resource_dec(dev_priv);
1518 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1520 vmw_fifo_resource_inc(dev_priv);
1521 WARN_ON(vmw_request_device_late(dev_priv));
1522 dev_priv->suspend_locked = false;
1523 if (dev_priv->suspend_state)
1528 vmw_fence_fifo_down(dev_priv->fman);
1529 __vmw_svga_disable(dev_priv);
1531 vmw_release_device_late(dev_priv);
1539 struct vmw_private *dev_priv = vmw_priv(dev);
1542 vmw_detect_version(dev_priv);
1544 vmw_fifo_resource_inc(dev_priv);
1546 ret = vmw_request_device(dev_priv);
1550 __vmw_svga_enable(dev_priv);
1552 vmw_fence_fifo_up(dev_priv->fman);
1553 dev_priv->suspend_locked = false;
1554 if (dev_priv->suspend_state)
1555 vmw_kms_resume(&dev_priv->drm);