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Searched refs:ddr50 (Results 1 – 25 of 39) sorted by relevance

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/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-st.txt57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
109 sd-uhs-ddr50;
/linux/arch/arm64/boot/dts/broadcom/
H A Dbcm2712-rpi-5-b-base.dtsi170 sd-uhs-ddr50;
180 sd-uhs-ddr50;
/linux/arch/arm/boot/dts/st/
H A Dstih418-b2199.dts94 sd-uhs-ddr50;
H A Dstm32mp157c-ed1.dts380 sd-uhs-ddr50;
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra72-evm.dts94 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
H A Ddra72-evm-revc.dts124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
H A Ddra7-evm.dts389 …pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50"…
H A Ddra72x-mmc-iodelay.dtsi90 mmc1_pins_ddr50_rev10: mmc1-ddr50-rev10-pins {
101 mmc1_pins_ddr50_rev20: mmc1-ddr50-rev20-pins {
H A Ddra71-evm.dts203 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
H A Ddra76x-mmc-iodelay.dtsi63 mmc1_pins_ddr50: mmc1-ddr50-pins {
/linux/arch/arm64/boot/dts/amd/
H A Delba.dtsi181 cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>;
/linux/arch/mips/boot/dts/mobileye/
H A Deyeq6h.dtsi121 sd-uhs-ddr50;
H A Deyeq5.dtsi266 sd-uhs-ddr50;
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxl-s905x-libretech-cc-v2.dts253 sd-uhs-ddr50;
H A Dmeson-gx-libretech-pc.dtsi378 sd-uhs-ddr50;
H A Dmeson-gxbb-nanopi-k2.dts349 sd-uhs-ddr50;
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-phg.dts243 sd-uhs-ddr50;
/linux/include/linux/
H A Drtsx_pci.h1304 #define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \ argument
1305 (((ddr50) << 16) | ((sdr50) << 8) | (sdr104))
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-sck-kv-g-revB.dtso176 clk-phase-uhs-ddr50 = <126>, <48>;
/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-firefly-reload.dts265 sd-uhs-ddr50;
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-skov-cpu.dtsi336 sd-uhs-ddr50;
/linux/arch/powerpc/boot/dts/
H A Dfsp2.dts506 sd-uhs-ddr50;
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62p-j722s-common-main.dtsi623 ti,otap-del-sel-ddr50 = <0x9>;
646 ti,otap-del-sel-ddr50 = <0x9>;
H A Dk3-am62a-main.dtsi622 ti,otap-del-sel-ddr50 = <0x9>;
645 ti,otap-del-sel-ddr50 = <0x9>;
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420-arndale-octa.dts813 sd-uhs-ddr50;

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