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Searched refs:config_base (Results 1 – 25 of 69) sorted by relevance

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/linux/drivers/perf/
H A Darm_v7_pmu.c866 armv7_pmnc_write_evtsel(idx, hwc->config_base); in armv7pmu_enable_event()
966 unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT; in armv7pmu_get_event_idx()
1001 unsigned long config_base = 0; in armv7pmu_set_event_filter() local
1008 config_base |= ARMV7_EXCLUDE_USER; in armv7pmu_set_event_filter()
1010 config_base |= ARMV7_EXCLUDE_PL1; in armv7pmu_set_event_filter()
1012 config_base |= ARMV7_INCLUDE_HYP; in armv7pmu_set_event_filter()
1018 event->config_base = config_base; in armv7pmu_set_event_filter()
1347 static void krait_evt_setup(int idx, u32 config_base) in krait_evt_setup() argument
1352 unsigned int region = EVENT_REGION(config_base); in krait_evt_setup()
1353 unsigned int group = EVENT_GROUP(config_base); in krait_evt_setup()
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H A Dapple_m1_cpu_pmu.c408 static void m1_pmu_configure_counter(unsigned int index, unsigned long config_base) in m1_pmu_configure_counter() argument
410 bool kernel = config_base & M1_PMU_CFG_COUNT_KERNEL; in m1_pmu_configure_counter()
411 bool guest = config_base & M1_PMU_CFG_COUNT_GUEST; in m1_pmu_configure_counter()
412 bool host = config_base & M1_PMU_CFG_COUNT_HOST; in m1_pmu_configure_counter()
413 bool user = config_base & M1_PMU_CFG_COUNT_USER; in m1_pmu_configure_counter()
414 u8 evt = config_base & M1_PMU_CFG_EVENT; in m1_pmu_configure_counter()
427 evt = event->hw.config_base & M1_PMU_CFG_EVENT; in m1_pmu_enable_event()
428 user = event->hw.config_base & M1_PMU_CFG_COUNT_USER; in m1_pmu_enable_event()
429 kernel = event->hw.config_base & M1_PMU_CFG_COUNT_KERNEL; in m1_pmu_enable_event()
431 m1_pmu_configure_counter(event->hw.idx, event->hw.config_base); in m1_pmu_enable_event()
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H A Darm_xscale_pmu.c216 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | in xscale1pmu_enable_event()
221 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | in xscale1pmu_enable_event()
270 if (XSCALE_PERFCTR_CCNT == hwc->config_base) { in xscale1pmu_get_event_idx()
551 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT; in xscale2pmu_enable_event()
556 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT; in xscale2pmu_enable_event()
561 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT; in xscale2pmu_enable_event()
566 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT; in xscale2pmu_enable_event()
H A Darm_pmuv3.c670 armv8pmu_write_evtype(idx - 1, hwc->config_base); in armv8pmu_write_event_type()
674 write_pmccfiltr(hwc->config_base); in armv8pmu_write_event_type()
676 write_pmicfiltr(hwc->config_base); in armv8pmu_write_event_type()
678 armv8pmu_write_evtype(idx, hwc->config_base); in armv8pmu_write_event_type()
986 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; in armv8pmu_can_use_pmccntr()
1022 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; in armv8pmu_get_event_idx()
1093 unsigned long config_base = 0; in armv8pmu_set_event_filter() local
1119 config_base |= ARMV8_PMU_INCLUDE_EL2; in armv8pmu_set_event_filter()
1121 config_base |= ARMV8_PMU_EXCLUDE_EL1; in armv8pmu_set_event_filter()
1123 config_base |= ARMV8_PMU_EXCLUDE_EL0; in armv8pmu_set_event_filter()
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H A Dthunderx2_pmu.c332 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_l3c()
347 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_dmc()
362 hwc->config_base = (unsigned long)tx2_pmu->base in init_cntr_base_ccpi2()
378 reg_writel(val, hwc->config_base); in uncore_start_event_l3c()
385 reg_writel(0, event->hw.config_base); in uncore_stop_event_l3c()
405 val = reg_readl(hwc->config_base); in uncore_start_event_dmc()
408 reg_writel(val, hwc->config_base); in uncore_start_event_dmc()
425 val = reg_readl(hwc->config_base); in uncore_stop_event_dmc()
427 reg_writel(val, hwc->config_base); in uncore_stop_event_dmc()
445 GET_EVENTID(event, emask)), hwc->config_base); in uncore_start_event_ccpi2()
H A Dqcom_l2_pmu.c347 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) { in l2_cache_get_event_idx()
364 group = L2_EVT_GROUP(hwc->config_base); in l2_cache_get_event_idx()
381 if (hwc->config_base != L2CYCLE_CTR_RAW_CODE) in l2_cache_clear_event_idx()
382 clear_bit(L2_EVT_GROUP(hwc->config_base), cluster->used_groups); in l2_cache_clear_event_idx()
530 hwc->config_base = event->attr.config; in l2_cache_event_init()
555 if (hwc->config_base == L2CYCLE_CTR_RAW_CODE) { in l2_cache_event_start()
558 config = hwc->config_base; in l2_cache_event_start()
H A Darm_v6_pmu.c216 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) | in armv6pmu_enable_event()
220 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) | in armv6pmu_enable_event()
318 if (ARMV6_PERFCTR_CPU_CYCLES == hwc->config_base) { in armv6pmu_get_event_idx()
H A Darm-ccn.c673 hw->config_base = bit; in arm_ccn_pmu_event_alloc()
694 clear_bit(hw->config_base, source->xp.dt_cmp_mask); in arm_ccn_pmu_event_release()
696 clear_bit(hw->config_base, source->pmu_events_mask); in arm_ccn_pmu_event_release()
940 unsigned long wp = hw->config_base; in arm_ccn_pmu_xp_watchpoint_config()
990 hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base); in arm_ccn_pmu_xp_event_config()
998 CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); in arm_ccn_pmu_xp_event_config()
999 val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); in arm_ccn_pmu_xp_event_config()
1014 hw->config_base); in arm_ccn_pmu_node_event_config()
1034 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base)); in arm_ccn_pmu_node_event_config()
1036 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base); in arm_ccn_pmu_node_event_config()
/linux/arch/arm/mach-bcm/
H A Dbcm63xx_smp.c37 unsigned long config_base; in scu_a9_enable() local
47 config_base = scu_a9_get_base(); in scu_a9_enable()
48 if (!config_base) { in scu_a9_enable()
53 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
56 config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
H A Dplatsmp.c49 unsigned long config_base; in scu_a9_enable() local
58 config_base = scu_a9_get_base(); in scu_a9_enable()
59 if (!config_base) { in scu_a9_enable()
64 scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
67 config_base, CORTEX_A9_SCU_SIZE); in scu_a9_enable()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pmu.c219 hwc->config_base = AMDGPU_PMU_PERF_TYPE_NONE; in amdgpu_perf_event_init()
243 switch (hwc->config_base) { in amdgpu_perf_start()
281 switch (hwc->config_base) { in amdgpu_perf_read()
311 switch (hwc->config_base) { in amdgpu_perf_stop()
346 hwc->config_base = AMDGPU_PMU_EVENT_CONFIG_TYPE_DF; in amdgpu_perf_add()
349 hwc->config_base = (hwc->config >> in amdgpu_perf_add()
357 switch (hwc->config_base) { in amdgpu_perf_add()
395 switch (hwc->config_base) { in amdgpu_perf_del()
/linux/drivers/pci/controller/dwc/
H A Dpcie-tegra194-acpi.c17 void __iomem *config_base; member
31 pcie_ecam->config_base = cfg->win; in tegra194_acpi_init()
99 return pcie_ecam->config_base + where; in tegra194_map_bus()
/linux/arch/x86/events/intel/
H A Duncore_discovery.c506 wrmsrq(hwc->config_base, hwc->config); in intel_generic_uncore_msr_enable_event()
514 wrmsrq(hwc->config_base, 0); in intel_generic_uncore_msr_disable_event()
536 hwc->config_base = uncore_pci_event_ctl(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
547 hwc->config_base = box_ctl + uncore_pci_event_ctl(box, hwc->idx); in intel_generic_uncore_assign_hw_event()
552 hwc->config_base = box_ctl + box->pmu->type->event_ctl + hwc->idx; in intel_generic_uncore_assign_hw_event()
594 pci_write_config_dword(pdev, hwc->config_base, hwc->config); in intel_generic_uncore_pci_enable_event()
603 pci_write_config_dword(pdev, hwc->config_base, 0); in intel_generic_uncore_pci_disable_event()
684 writel(hwc->config, box->io_addr + hwc->config_base); in intel_generic_uncore_mmio_enable_event()
695 writel(0, box->io_addr + hwc->config_base); in intel_generic_uncore_mmio_disable_event()
H A Duncore_nhmex.c244 wrmsrq(event->hw.config_base, 0); in nhmex_uncore_msr_disable_event()
252 wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
254 wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
256 wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
389 wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | in nhmex_bbox_msr_enable_event()
476 wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_sbox_msr_enable_event()
864 wrmsrq(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_mbox_msr_enable_event()
1149 wrmsrq(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 | in nhmex_rbox_msr_enable_event()
H A Dknc.c186 (void)wrmsrq_safe(hwc->config_base + hwc->idx, val); in knc_pmu_disable_event()
197 (void)wrmsrq_safe(hwc->config_base + hwc->idx, val); in knc_pmu_enable_event()
H A Duncore_snbep.c607 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in snbep_uncore_pci_enable_event()
615 pci_write_config_dword(pdev, hwc->config_base, hwc->config); in snbep_uncore_pci_disable_event()
672 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in snbep_uncore_msr_enable_event()
680 wrmsrq(hwc->config_base, hwc->config); in snbep_uncore_msr_disable_event()
1214 pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in snbep_qpi_enable_event()
1775 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in ivbep_cbox_enable_event()
2286 pci_write_config_dword(pdev, hwc->config_base, in knl_uncore_imc_enable_event()
2289 pci_write_config_dword(pdev, hwc->config_base, in knl_uncore_imc_enable_event()
2759 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in hswep_cbox_enable_event()
3647 wrmsrq(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); in skx_iio_enable_event()
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/linux/arch/x86/events/zhaoxin/
H A Dcore.c297 rdmsrq(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
299 wrmsrq(hwc->config_base, ctrl_val); in zhaoxin_pmu_disable_fixed()
306 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in zhaoxin_pmu_disable_event()
333 rdmsrq(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
336 wrmsrq(hwc->config_base, ctrl_val); in zhaoxin_pmu_enable_fixed()
343 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) { in zhaoxin_pmu_enable_event()
/linux/arch/loongarch/kernel/
H A Dperf_event.c275 (evt->config_base & M_PERFCTL_CONFIG_MASK) | CSR_PERFCTRL_IE; in loongarch_pmu_enable_event()
784 hwc->config_base = CSR_PERFCTRL_IE; in __hw_perf_event_init()
791 hwc->config_base |= CSR_PERFCTRL_PLV3; in __hw_perf_event_init()
792 hwc->config_base |= CSR_PERFCTRL_PLV2; in __hw_perf_event_init()
795 hwc->config_base |= CSR_PERFCTRL_PLV0; in __hw_perf_event_init()
798 hwc->config_base |= CSR_PERFCTRL_PLV1; in __hw_perf_event_init()
801 hwc->config_base &= M_PERFCTL_CONFIG_MASK; in __hw_perf_event_init()
/linux/arch/s390/kernel/
H A Dperf_cpum_cf.c811 hwc->config_base = cpumf_ctr_ctl[set]; in __hw_perf_event_init()
829 if (!(hwc->config_base & cpumf_ctr_info.auth_ctl)) in __hw_perf_event_init()
930 ctr_set_enable(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
931 ctr_set_start(&cpuhw->state, hwc->config_base); in cpumf_pmu_start()
941 hwc->config_base, true); in cpumf_pmu_start()
948 if ((hwc->config_base & cpumf_ctr_ctl[i])) in cpumf_pmu_start()
998 if (!(hwc->config_base & cpumf_ctr_ctl[i])) in cpumf_pmu_stop()
1011 event->hw.config_base, in cpumf_pmu_stop()
1013 if (cfdiag_diffctr(cpuhw, event->hw.config_base)) in cpumf_pmu_stop()
1026 ctr_set_enable(&cpuhw->state, event->hw.config_base); in cpumf_pmu_add()
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/linux/arch/powerpc/perf/
H A Dcore-fsl-emb.c327 write_pmlca(i, event->hw.config_base); in fsl_emb_pmu_add()
536 event->hw.config_base = PMLCA_CE | PMLCA_FCM1 | in fsl_emb_pmu_event_init()
540 event->hw.config_base |= PMLCA_FCU; in fsl_emb_pmu_event_init()
542 event->hw.config_base |= PMLCA_FCS; in fsl_emb_pmu_event_init()
/linux/drivers/pci/controller/
H A Dpci-v3-semi.c239 void __iomem *config_base; member
378 return v3->config_base + address + offset; in v3_map_bus()
757 v3->config_base = devm_ioremap_resource(dev, regs); in v3_pci_probe()
758 if (IS_ERR(v3->config_base)) in v3_pci_probe()
759 return PTR_ERR(v3->config_base); in v3_pci_probe()
/linux/arch/alpha/kernel/
H A Dperf_event.c200 event[0]->hw.config_base = config; in ev67_check_constraints()
203 event[1]->hw.config_base = config; in ev67_check_constraints()
424 cpuc->config = cpuc->event[0]->hw.config_base; in maybe_change_configuration()
663 hwc->config_base = 0; in __hw_perf_event_init()
/linux/arch/x86/events/amd/
H A Dibs.c369 hwc->config_base = perf_ibs->msr; in perf_ibs_init()
428 rdmsrq(event->hw.config_base, *config); in perf_ibs_event_update()
439 wrmsrq(hwc->config_base, tmp & ~perf_ibs->enable_mask); in perf_ibs_enable_event()
441 wrmsrq(hwc->config_base, tmp | perf_ibs->enable_mask); in perf_ibs_enable_event()
456 wrmsrq(hwc->config_base, config); in perf_ibs_disable_event()
458 wrmsrq(hwc->config_base, config); in perf_ibs_disable_event()
517 rdmsrq(hwc->config_base, config); in perf_ibs_stop()
1258 msr = hwc->config_base; in perf_ibs_handle_irq()
/linux/arch/mips/kernel/
H A Dperf_event_mipsxx.c358 (evt->config_base & M_PERFCTL_CONFIG_MASK) | in mipsxx_pmu_enable_event()
363 (evt->config_base & M_PERFCTL_CONFIG_MASK) | in mipsxx_pmu_enable_event()
1503 hwc->config_base = MIPS_PERFCTRL_IE; in __hw_perf_event_init()
1510 hwc->config_base |= MIPS_PERFCTRL_U; in __hw_perf_event_init()
1512 hwc->config_base |= MIPS_PERFCTRL_K; in __hw_perf_event_init()
1514 hwc->config_base |= MIPS_PERFCTRL_EXL; in __hw_perf_event_init()
1517 hwc->config_base |= MIPS_PERFCTRL_S; in __hw_perf_event_init()
1519 hwc->config_base &= M_PERFCTL_CONFIG_MASK; in __hw_perf_event_init()
/linux/drivers/pci/controller/plda/
H A Dpcie-plda-host.c28 return pcie->config_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in plda_pcie_map_bus()
595 port->config_base = devm_ioremap_resource(dev, cfg_res); in plda_pcie_host_init()
596 if (IS_ERR(port->config_base)) in plda_pcie_host_init()
597 return dev_err_probe(dev, PTR_ERR(port->config_base), in plda_pcie_host_init()

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