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Searched refs:cmdq_pkt (Results 1 – 23 of 23) sorted by relevance

/linux/include/linux/soc/mediatek/
H A Dmtk-cmdq.h28 struct cmdq_pkt;
67 int (*pkt_write)(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base,
69 int (*pkt_write_mask)(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base,
118 int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size);
125 void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt);
136 int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
148 int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
161 int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys,
174 int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
188 int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/,
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H A Dmtk-mmsys.h98 int height, struct cmdq_pkt *cmdq_pkt);
101 struct cmdq_pkt *cmdq_pkt);
104 u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt);
107 struct cmdq_pkt *cmdq_pkt);
110 struct cmdq_pkt *cmdq_pkt);
113 struct cmdq_pkt *cmdq_pkt);
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_disp_drv.h19 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
30 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
39 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
44 unsigned int dither_en, struct cmdq_pkt *cmdq_pkt);
58 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
68 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
73 struct cmdq_pkt *cmdq_pkt);
74 void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);
75 void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);
86 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
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H A Dmtk_disp_merge.c83 void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt) in mtk_merge_start_cmdq() argument
88 mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs, in mtk_merge_start_cmdq()
91 mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, in mtk_merge_start_cmdq()
95 void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt) in mtk_merge_stop_cmdq() argument
100 mtk_ddp_write(cmdq_pkt, 0x1, &priv->cmdq_reg, priv->regs, in mtk_merge_stop_cmdq()
103 mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, in mtk_merge_stop_cmdq()
106 if (!cmdq_pkt && priv->async_clk) in mtk_merge_stop_cmdq()
111 struct cmdq_pkt *cmdq_pkt) in mtk_merge_fifo_setting() argument
113 mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN, in mtk_merge_fifo_setting()
116 mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE, in mtk_merge_fifo_setting()
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H A Dmtk_mdp_rdma.c149 static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt) in mtk_mdp_rdma_fifo_config() argument
153 mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN | VAL_PRE_ULTRA_EN_ENABLE << 16 | in mtk_mdp_rdma_fifo_config()
161 void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt) in mtk_mdp_rdma_start() argument
165 mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg, in mtk_mdp_rdma_start()
169 void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt) in mtk_mdp_rdma_stop() argument
173 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, in mtk_mdp_rdma_stop()
175 mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET); in mtk_mdp_rdma_stop()
176 mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, MDP_RDMA_RESET); in mtk_mdp_rdma_stop()
180 struct cmdq_pkt *cmdq_pkt) in mtk_mdp_rdma_config() argument
188 mtk_mdp_rdma_fifo_config(dev, cmdq_pkt); in mtk_mdp_rdma_config()
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H A Dmtk_ddp_comp.c69 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, in mtk_ddp_write() argument
74 if (cmdq_pkt) in mtk_ddp_write()
75 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write()
82 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, in mtk_ddp_write_relaxed() argument
87 if (cmdq_pkt) in mtk_ddp_write_relaxed()
88 cmdq_pkt_write(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_relaxed()
95 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, in mtk_ddp_write_mask() argument
100 if (cmdq_pkt) { in mtk_ddp_write_mask()
101 cmdq_pkt_write_mask(cmdq_pkt, cmdq_reg->subsys, in mtk_ddp_write_mask()
130 unsigned int dither_en, struct cmdq_pkt *cmdq_pkt) in mtk_dither_set_common() argument
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H A Dmtk_ethdr.c157 struct cmdq_pkt *cmdq_pkt) in mtk_ethdr_layer_config() argument
178 mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); in mtk_ethdr_layer_config()
204 MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt); in mtk_ethdr_layer_config()
206 mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base, in mtk_ethdr_layer_config()
208 mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx)); in mtk_ethdr_layer_config()
209 mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx)); in mtk_ethdr_layer_config()
210 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, in mtk_ethdr_layer_config()
216 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_ethdr_config() argument
228 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base, in mtk_ethdr_config()
231 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base, in mtk_ethdr_config()
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H A Dmtk_disp_ovl.c288 static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt, in mtk_ovl_set_afbc() argument
291 mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0, in mtk_ovl_set_afbc()
297 struct cmdq_pkt *cmdq_pkt) in mtk_ovl_set_bit_depth() argument
308 mtk_ddp_write_mask(cmdq_pkt, OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx), in mtk_ovl_set_bit_depth()
315 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_ovl_config() argument
320 mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_config()
327 mtk_ddp_write_relaxed(cmdq_pkt, OVL_COLOR_ALPHA, &ovl->cmdq_reg, in mtk_ovl_config()
330 mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); in mtk_ovl_config()
331 mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); in mtk_ovl_config()
369 struct cmdq_pkt *cmdq_pkt) in mtk_ovl_layer_on() argument
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H A Dmtk_disp_ccorr.c59 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_ccorr_config() argument
63 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
65 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs, in mtk_ccorr_config()
91 struct cmdq_pkt *cmdq_pkt = NULL; in mtk_ccorr_ctm_set() local
103 mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], in mtk_ccorr_ctm_set()
105 mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], in mtk_ccorr_ctm_set()
107 mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], in mtk_ccorr_ctm_set()
109 mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], in mtk_ccorr_ctm_set()
111 mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, in mtk_ccorr_ctm_set()
H A Dmtk_ddp_comp.h50 struct cmdq_pkt;
58 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
74 struct cmdq_pkt *cmdq_pkt);
146 struct cmdq_pkt *cmdq_pkt) in mtk_ddp_comp_config() argument
149 comp->funcs->config(comp->dev, w, h, vrefresh, bpc, cmdq_pkt); in mtk_ddp_comp_config()
224 struct cmdq_pkt *cmdq_pkt) in mtk_ddp_comp_layer_config() argument
227 comp->funcs->layer_config(comp->dev, idx, state, cmdq_pkt); in mtk_ddp_comp_layer_config()
356 void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
359 void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
362 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
H A Dmtk_disp_rdma.c186 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_rdma_config() argument
193 mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_config()
195 mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_config()
213 mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON); in mtk_rdma_config()
260 struct cmdq_pkt *cmdq_pkt) in mtk_rdma_layer_config() argument
270 mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON); in mtk_rdma_layer_config()
273 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
276 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB, in mtk_rdma_layer_config()
280 mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
284 mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
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H A Dmtk_disp_ovl_adaptor.c134 struct cmdq_pkt *cmdq_pkt) in mtk_ovl_adaptor_layer_config() argument
161 mtk_merge_stop_cmdq(merge, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
162 mtk_mdp_rdma_stop(rdma_l, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
163 mtk_mdp_rdma_stop(rdma_r, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
164 mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
180 mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
182 pending->height, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
190 mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
195 mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
198 mtk_merge_start_cmdq(merge, cmdq_pkt); in mtk_ovl_adaptor_layer_config()
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H A Dmtk_ethdr.h15 unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
19 struct cmdq_pkt *cmdq_pkt);
H A Dmtk_disp_color.c62 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_color_config() argument
66 mtk_ddp_write(cmdq_pkt, w, &color->cmdq_reg, color->regs, DISP_COLOR_WIDTH(color)); in mtk_color_config()
67 mtk_ddp_write(cmdq_pkt, h, &color->cmdq_reg, color->regs, DISP_COLOR_HEIGHT(color)); in mtk_color_config()
H A Dmtk_disp_aal.c69 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_aal_config() argument
77 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); in mtk_aal_config()
78 mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); in mtk_aal_config()
H A Dmtk_disp_gamma.c211 unsigned int bpc, struct cmdq_pkt *cmdq_pkt) in mtk_gamma_config() argument
219 mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZE); in mtk_gamma_config()
222 DISP_GAMMA_CFG, GAMMA_DITHERING, cmdq_pkt); in mtk_gamma_config()
H A Dmtk_crtc.c56 struct cmdq_pkt cmdq_handle;
486 struct cmdq_pkt *cmdq_handle) in mtk_crtc_ddp_config()
561 struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle; in mtk_crtc_update_config()
/linux/drivers/soc/mediatek/
H A Dmtk-mmsys.c164 struct cmdq_pkt *cmdq_pkt) in mtk_mmsys_update_bits() argument
169 if (mmsys->cmdq_base.size && cmdq_pkt) { in mtk_mmsys_update_bits()
170 ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, in mtk_mmsys_update_bits()
217 struct cmdq_pkt *cmdq_pkt) in mtk_mmsys_merge_async_config() argument
220 ~0, height << 16 | width, cmdq_pkt); in mtk_mmsys_merge_async_config()
225 struct cmdq_pkt *cmdq_pkt) in mtk_mmsys_hdr_config() argument
228 be_height << 16 | be_width, cmdq_pkt); in mtk_mmsys_hdr_config()
233 u8 mode, u32 biwidth, struct cmdq_pkt *cmdq_pkt) in mtk_mmsys_mixer_in_config() argument
238 alpha << 16 | alpha, cmdq_pkt); in mtk_mmsys_mixer_in_config()
239 mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(15 + idx), 0, cmdq_pkt); in mtk_mmsys_mixer_in_config()
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H A Dmtk-cmdq-helper.c147 int cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt, size_t size) in cmdq_pkt_create()
174 void cmdq_pkt_destroy(struct cmdq_client *client, struct cmdq_pkt *pkt) in cmdq_pkt_destroy()
182 static int cmdq_pkt_append_command(struct cmdq_pkt *pkt, in cmdq_pkt_append_command()
209 static int cmdq_pkt_mask(struct cmdq_pkt *pkt, u32 mask) in cmdq_pkt_mask()
218 int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value) in cmdq_pkt_write()
230 int cmdq_pkt_write_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/, u32 pa_base, in cmdq_pkt_write_pa()
243 int cmdq_pkt_write_subsys(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base /*unused*/, in cmdq_pkt_write_subsys()
250 int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys, in cmdq_pkt_write_mask()
267 int cmdq_pkt_write_mask_pa(struct cmdq_pkt *pkt, u8 subsys /*unused*/, u32 pa_base, in cmdq_pkt_write_mask_pa()
281 int cmdq_pkt_write_mask_subsys(struct cmdq_pkt *pkt, u8 subsys, u32 pa_base /*unused*/, in cmdq_pkt_write_mask_subsys()
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H A Dmtk-mutex.c992 struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt; in mtk_mutex_enable_by_cmdq() local
1001 cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys, in mtk_mutex_enable_by_cmdq()
/linux/include/linux/mailbox/
H A Dmtk-cmdq-mailbox.h70 struct cmdq_pkt *pkt;
78 struct cmdq_pkt { struct
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmtk-mdp3-cmdq.h27 struct cmdq_pkt pkt;
/linux/drivers/mailbox/
H A Dmtk-cmdq-mailbox.c81 struct cmdq_pkt *pkt; /* the packet sent from mailbox client */
449 struct cmdq_pkt *pkt = (struct cmdq_pkt *)data; in cmdq_mbox_send_data()