Searched refs:clk_select (Results 1 – 5 of 5) sorted by relevance
39 enum fsl_pwm_clk clk_select; member78 if (a->clk_select != b->clk_select) in fsl_pwm_periodcfg_are_equal()115 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]); in fsl_pwm_ticks_to_ns()143 periodcfg->clk_select = index; in fsl_pwm_calculate_period_clk()255 if (fpc->period.clk_select != periodcfg.clk_select) { in fsl_pwm_apply_config()257 enum fsl_pwm_clk oldclk = fpc->period.clk_select; in fsl_pwm_apply_config()258 enum fsl_pwm_clk newclk = periodcfg.clk_select; in fsl_pwm_apply_config()272 FTM_SC_CLK(periodcfg.clk_select)); in fsl_pwm_apply_config()318 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()330 ret = clk_prepare_enable(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()[all …]
112 u32 clk_select; member768 tmr_ctrl = FIELD_PREP(TMR_CTRL_CK_SEL, priv->clk_select) | in netc_timer_init()855 priv->clk_select = NETC_TMR_SYSTEM_CLK; in netc_timer_get_reference_clk_source()869 priv->clk_select = i ? NETC_TMR_EXT_OSC : in netc_timer_get_reference_clk_source()
1580 PPCLK_e clk_select = 0; in vega12_display_clock_voltage_request() local1586 clk_select = PPCLK_DCEFCLK; in vega12_display_clock_voltage_request()1589 clk_select = PPCLK_DISPCLK; in vega12_display_clock_voltage_request()1592 clk_select = PPCLK_PIXCLK; in vega12_display_clock_voltage_request()1595 clk_select = PPCLK_PHYCLK; in vega12_display_clock_voltage_request()1604 clk_request = (clk_select << 16) | clk_freq; in vega12_display_clock_voltage_request()
2305 PPCLK_e clk_select = 0; in vega20_display_clock_voltage_request() local2311 clk_select = PPCLK_DCEFCLK; in vega20_display_clock_voltage_request()2314 clk_select = PPCLK_DISPCLK; in vega20_display_clock_voltage_request()2317 clk_select = PPCLK_PIXCLK; in vega20_display_clock_voltage_request()2320 clk_select = PPCLK_PHYCLK; in vega20_display_clock_voltage_request()2329 clk_request = (clk_select << 16) | clk_freq; in vega20_display_clock_voltage_request()
4042 DSPCLK_e clk_select = 0; in vega10_display_clock_voltage_request() local4047 clk_select = DSPCLK_DCEFCLK; in vega10_display_clock_voltage_request()4050 clk_select = DSPCLK_DISPCLK; in vega10_display_clock_voltage_request()4053 clk_select = DSPCLK_PIXCLK; in vega10_display_clock_voltage_request()4056 clk_select = DSPCLK_PHYCLK; in vega10_display_clock_voltage_request()4065 clk_request = (clk_freq << 16) | clk_select; in vega10_display_clock_voltage_request()