Searched refs:MES (Results 1 – 2 of 2) sorted by relevance
| /linux/Documentation/gpu/amdgpu/gc/ |
| H A D | mes.rst | 4 MicroEngine Scheduler (MES)
18 Scheduler (MES). Whenever the driver is initialized, it creates one MQD per
19 hardware queue, and then the MQDs are handed to the MES firmware for mapping
34 In terms of User Queues, MES can dynamically map them to the HQD. If there are
35 more MQDs than HQDs, the MES firmware will preempt other user queues to make
36 sure each queues get a time slice; in other words, MES is a microcontroller
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| /linux/drivers/infiniband/hw/hfi1/ |
| H A D | chip.c | 343 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK macro
345 /* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY)),
346 /* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR)),
347 /* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR)),
348 /* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED)),
349 /* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH)),
350 /* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED)),
351 /* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY)),
352 /* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR)),
353 /* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE)),
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