Searched refs:MDIO_START (Results 1 – 7 of 7) sorted by relevance
26 #define MDIO_START BIT(23) macro 55 MDIO_START | MDIO_RD_NWR; in emac_mdio_read() 60 !(reg & (MDIO_START | MDIO_BUSY)), in emac_mdio_read() 79 MDIO_START; in emac_mdio_write() 84 !(reg & (MDIO_START | MDIO_BUSY)), in emac_mdio_write()
206 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | in atl1e_read_phy_reg() 216 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1e_read_phy_reg() 220 if (!(val & (MDIO_START | MDIO_BUSY))) { in atl1e_read_phy_reg() 242 MDIO_START | in atl1e_write_phy_reg() 251 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1e_write_phy_reg() 256 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1e_write_phy_reg() 392 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1e_phy_commit() 396 if (0 != (val & (MDIO_START | MDIO_BUSY))) { in atl1e_phy_commit()
223 #define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/ macro
2466 MDIO_START | in atl2_read_phy_reg() 2477 if (!(val & (MDIO_START | MDIO_BUSY))) in atl2_read_phy_reg() 2481 if (!(val & (MDIO_START | MDIO_BUSY))) { in atl2_read_phy_reg() 2503 MDIO_START | in atl2_write_phy_reg() 2512 if (!(val & (MDIO_START | MDIO_BUSY))) in atl2_write_phy_reg() 2518 if (!(val & (MDIO_START | MDIO_BUSY))) in atl2_write_phy_reg() 2610 if (!(val & (MDIO_START | MDIO_BUSY))) in atl2_phy_commit() 2614 if (0 != (val & (MDIO_START | MDIO_BUSY))) { in atl2_phy_commit()
163 #define MDIO_START 0x800000 macro
346 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 << in atl1_read_phy_reg() 354 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1_read_phy_reg() 357 if (!(val & (MDIO_START | MDIO_BUSY))) { in atl1_read_phy_reg() 595 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; in atl1_write_phy_reg() 602 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1_write_phy_reg() 606 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1_write_phy_reg() 675 if (!(val & (MDIO_START | MDIO_BUSY))) in atl1_phy_reset() 679 if ((val & (MDIO_START | MDIO_BUSY)) != 0) { in atl1_phy_reset()
48 #define MDIO_START BIT(20) macro 50 #define MDIO_READ (BIT(17) | MDIO_START)51 #define MDIO_WRITE (BIT(16) | MDIO_START)924 for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) { in hix5hd2_mdio_wait_ready()