1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 *
6 * Authors:
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 */
10
11 #ifndef _UFSHCI_H
12 #define _UFSHCI_H
13
14 #include <linux/types.h>
15 #include <ufs/ufs.h>
16
17 enum {
18 TASK_REQ_UPIU_SIZE_DWORDS = 8,
19 TASK_RSP_UPIU_SIZE_DWORDS = 8,
20 ALIGNED_UPIU_SIZE = 512,
21 };
22
23 /* UFSHCI Registers */
24 enum {
25 REG_CONTROLLER_CAPABILITIES = 0x00,
26 REG_MCQCAP = 0x04,
27 REG_UFS_VERSION = 0x08,
28 REG_EXT_CONTROLLER_CAPABILITIES = 0x0C,
29 REG_CONTROLLER_PID = 0x10,
30 REG_CONTROLLER_MID = 0x14,
31 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
32 REG_INTERRUPT_STATUS = 0x20,
33 REG_INTERRUPT_ENABLE = 0x24,
34 REG_CONTROLLER_STATUS = 0x30,
35 REG_CONTROLLER_ENABLE = 0x34,
36 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
37 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
38 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
39 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
40 REG_UIC_ERROR_CODE_DME = 0x48,
41 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
42 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
43 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
44 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
45 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
46 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
47 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
48 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
49 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
50 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
51 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
52 REG_UIC_COMMAND = 0x90,
53 REG_UIC_COMMAND_ARG_1 = 0x94,
54 REG_UIC_COMMAND_ARG_2 = 0x98,
55 REG_UIC_COMMAND_ARG_3 = 0x9C,
56
57 UFSHCI_REG_SPACE_SIZE = 0xA0,
58
59 REG_UFS_CCAP = 0x100,
60 REG_UFS_CRYPTOCAP = 0x104,
61
62 REG_UFS_MEM_CFG = 0x300,
63 REG_UFS_MCQ_CFG = 0x380,
64 REG_UFS_ESILBA = 0x384,
65 REG_UFS_ESIUBA = 0x388,
66 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
67 };
68
69 /* Controller capability masks */
70 enum {
71 MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F,
72 MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF,
73 MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00,
74 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
75 MASK_EHSLUTRD_SUPPORTED = 0x00400000,
76 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
77 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
78 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
79 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
80 MASK_CRYPTO_SUPPORT = 0x10000000,
81 MASK_LSDB_SUPPORT = 0x20000000,
82 MASK_MCQ_SUPPORT = 0x40000000,
83 };
84
85 enum {
86 /* Submission Queue (SQ) Configuration Registers */
87 REG_SQATTR = 0x0,
88 REG_SQLBA = 0x4,
89 REG_SQUBA = 0x8,
90 REG_SQDAO = 0xC,
91 REG_SQISAO = 0x10,
92
93 /* Completion Queue (CQ) Configuration Registers */
94 REG_CQATTR = 0x20,
95 REG_CQLBA = 0x24,
96 REG_CQUBA = 0x28,
97 REG_CQDAO = 0x2C,
98 REG_CQISAO = 0x30,
99 };
100
101 /* Operation and Runtime Registers - Submission Queues and Completion Queues */
102 enum {
103 REG_SQHP = 0x0,
104 REG_SQTP = 0x4,
105 REG_SQRTC = 0x8,
106 REG_SQCTI = 0xC,
107 REG_SQRTS = 0x10,
108 };
109
110 enum {
111 REG_CQHP = 0x0,
112 REG_CQTP = 0x4,
113 };
114
115 enum {
116 REG_CQIS = 0x0,
117 REG_CQIE = 0x4,
118 };
119
120 enum {
121 SQ_START = 0x0,
122 SQ_STOP = 0x1,
123 SQ_ICU = 0x2,
124 };
125
126 enum {
127 SQ_STS = 0x1,
128 SQ_CUS = 0x2,
129 };
130
131 #define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4)
132 #define UFS_MASK(mask, offset) ((mask) << (offset))
133
134 /* UFS Version 08h */
135 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
136 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
137
138 #define UFSHCD_NUM_RESERVED 1
139 /*
140 * Controller UFSHCI version
141 * - 2.x and newer use the following scheme:
142 * major << 8 + minor << 4
143 * - 1.x has been converted to match this in
144 * ufshcd_get_ufs_version()
145 */
ufshci_version(u32 major,u32 minor)146 static inline u32 ufshci_version(u32 major, u32 minor)
147 {
148 return (major << 8) + (minor << 4);
149 }
150
151 /*
152 * HCDDID - Host Controller Identification Descriptor
153 * - Device ID and Device Class 10h
154 */
155 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
156 #define DEVICE_ID UFS_MASK(0xFF, 24)
157
158 /*
159 * HCPMID - Host Controller Identification Descriptor
160 * - Product/Manufacturer ID 14h
161 */
162 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
163 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
164
165 /* AHIT - Auto-Hibernate Idle Timer */
166 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
167 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
168 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10
169 #define UFSHCI_AHIBERN8_MAX (1023 * 100000)
170
171 /*
172 * IS - Interrupt Status - 20h
173 */
174 #define UTP_TRANSFER_REQ_COMPL 0x1
175 #define UIC_DME_END_PT_RESET 0x2
176 #define UIC_ERROR 0x4
177 #define UIC_TEST_MODE 0x8
178 #define UIC_POWER_MODE 0x10
179 #define UIC_HIBERNATE_EXIT 0x20
180 #define UIC_HIBERNATE_ENTER 0x40
181 #define UIC_LINK_LOST 0x80
182 #define UIC_LINK_STARTUP 0x100
183 #define UTP_TASK_REQ_COMPL 0x200
184 #define UIC_COMMAND_COMPL 0x400
185 #define DEVICE_FATAL_ERROR 0x800
186 #define UTP_ERROR 0x1000
187 #define CONTROLLER_FATAL_ERROR 0x10000
188 #define SYSTEM_BUS_FATAL_ERROR 0x20000
189 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000
190 #define MCQ_CQ_EVENT_STATUS 0x100000
191
192 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
193 UIC_HIBERNATE_EXIT)
194
195 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
196 UIC_POWER_MODE)
197
198 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
199
200 #define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
201
202 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
203 CONTROLLER_FATAL_ERROR |\
204 SYSTEM_BUS_FATAL_ERROR |\
205 CRYPTO_ENGINE_FATAL_ERROR |\
206 UIC_LINK_LOST |\
207 UTP_ERROR)
208
209 /* HCS - Host Controller Status 30h */
210 #define DEVICE_PRESENT 0x1
211 #define UTP_TRANSFER_REQ_LIST_READY 0x2
212 #define UTP_TASK_REQ_LIST_READY 0x4
213 #define UIC_COMMAND_READY 0x8
214 #define HOST_ERROR_INDICATOR 0x10
215 #define DEVICE_ERROR_INDICATOR 0x20
216 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
217
218 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
219 UTP_TASK_REQ_LIST_READY |\
220 UIC_COMMAND_READY)
221
222 enum {
223 PWR_OK = 0x0,
224 PWR_LOCAL = 0x01,
225 PWR_REMOTE = 0x02,
226 PWR_BUSY = 0x03,
227 PWR_ERROR_CAP = 0x04,
228 PWR_FATAL_ERROR = 0x05,
229 };
230
231 /* HCE - Host Controller Enable 34h */
232 #define CONTROLLER_ENABLE 0x1
233 #define CONTROLLER_DISABLE 0x0
234 #define CRYPTO_GENERAL_ENABLE 0x2
235
236 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
237 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
238 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
239 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
240 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
241
242 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
243 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000
244 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
245 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
246 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
247 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
248 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
249 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
250 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
251 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
252
253 /* UECN - Host UIC Error Code Network Layer 40h */
254 #define UIC_NETWORK_LAYER_ERROR 0x80000000
255 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
256 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
257 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
258 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
259
260 /* UECT - Host UIC Error Code Transport Layer 44h */
261 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000
262 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
263 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
264 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
265 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
266 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
267 #define UIC_TRANSPORT_BAD_TC 0x10
268 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
269 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
270
271 /* UECDME - Host UIC Error Code DME 48h */
272 #define UIC_DME_ERROR 0x80000000
273 #define UIC_DME_ERROR_CODE_MASK 0x1
274
275 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
276 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
277 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
278 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
279 #define INT_AGGR_STATUS_BIT 0x100000
280 #define INT_AGGR_PARAM_WRITE 0x1000000
281 #define INT_AGGR_ENABLE 0x80000000
282
283 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
284 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
285
286 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
287 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
288
289 /* REG_UFS_MEM_CFG - Global Config Registers 300h */
290 #define MCQ_MODE_SELECT BIT(0)
291 #define ESI_ENABLE BIT(1)
292
293 /* CQISy - CQ y Interrupt Status Register */
294 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1
295
296 /* UICCMD - UIC Command */
297 #define COMMAND_OPCODE_MASK 0xFF
298 #define GEN_SELECTOR_INDEX_MASK 0xFFFF
299
300 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
301 #define RESET_LEVEL 0xFF
302
303 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
304 #define CONFIG_RESULT_CODE_MASK 0xFF
305 #define GENERIC_ERROR_CODE_MASK 0xFF
306
307 /* GenSelectorIndex calculation macros for M-PHY attributes */
308 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
309 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
310
311 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
312 ((sel) & 0xFFFF))
313 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
314 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
315 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
316
317 /* Link Status*/
318 enum link_status {
319 UFSHCD_LINK_IS_DOWN = 1,
320 UFSHCD_LINK_IS_UP = 2,
321 };
322
323 /* UIC Commands */
324 enum uic_cmd_dme {
325 UIC_CMD_DME_GET = 0x01,
326 UIC_CMD_DME_SET = 0x02,
327 UIC_CMD_DME_PEER_GET = 0x03,
328 UIC_CMD_DME_PEER_SET = 0x04,
329 UIC_CMD_DME_POWERON = 0x10,
330 UIC_CMD_DME_POWEROFF = 0x11,
331 UIC_CMD_DME_ENABLE = 0x12,
332 UIC_CMD_DME_RESET = 0x14,
333 UIC_CMD_DME_END_PT_RST = 0x15,
334 UIC_CMD_DME_LINK_STARTUP = 0x16,
335 UIC_CMD_DME_HIBER_ENTER = 0x17,
336 UIC_CMD_DME_HIBER_EXIT = 0x18,
337 UIC_CMD_DME_TEST_MODE = 0x1A,
338 };
339
340 /* UIC Config result code / Generic error code */
341 enum {
342 UIC_CMD_RESULT_SUCCESS = 0x00,
343 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
344 UIC_CMD_RESULT_FAILURE = 0x01,
345 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
346 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
347 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
348 UIC_CMD_RESULT_BAD_INDEX = 0x05,
349 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
350 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
351 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
352 UIC_CMD_RESULT_BUSY = 0x09,
353 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
354 };
355
356 #define MASK_UIC_COMMAND_RESULT 0xFF
357
358 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
359 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
360
361 /* Interrupt disable masks */
362 enum {
363 /* Interrupt disable mask for UFSHCI v1.1 */
364 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
365
366 /* Interrupt disable mask for UFSHCI v2.1 */
367 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
368 };
369
370 /* CCAP - Crypto Capability 100h */
371 union ufs_crypto_capabilities {
372 __le32 reg_val;
373 struct {
374 u8 num_crypto_cap;
375 u8 config_count;
376 u8 reserved;
377 u8 config_array_ptr;
378 };
379 };
380
381 enum ufs_crypto_key_size {
382 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
383 UFS_CRYPTO_KEY_SIZE_128 = 0x1,
384 UFS_CRYPTO_KEY_SIZE_192 = 0x2,
385 UFS_CRYPTO_KEY_SIZE_256 = 0x3,
386 UFS_CRYPTO_KEY_SIZE_512 = 0x4,
387 };
388
389 enum ufs_crypto_alg {
390 UFS_CRYPTO_ALG_AES_XTS = 0x0,
391 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
392 UFS_CRYPTO_ALG_AES_ECB = 0x2,
393 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
394 };
395
396 /* x-CRYPTOCAP - Crypto Capability X */
397 union ufs_crypto_cap_entry {
398 __le32 reg_val;
399 struct {
400 u8 algorithm_id;
401 u8 sdus_mask; /* Supported data unit size mask */
402 u8 key_size;
403 u8 reserved;
404 };
405 };
406
407 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
408 #define UFS_CRYPTO_KEY_MAX_SIZE 64
409 /* x-CRYPTOCFG - Crypto Configuration X */
410 union ufs_crypto_cfg_entry {
411 __le32 reg_val[32];
412 struct {
413 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
414 u8 data_unit_size;
415 u8 crypto_cap_idx;
416 u8 reserved_1;
417 u8 config_enable;
418 u8 reserved_multi_host;
419 u8 reserved_2;
420 u8 vsb[2];
421 u8 reserved_3[56];
422 };
423 };
424
425 /*
426 * Request Descriptor Definitions
427 */
428
429 /* To accommodate UFS2.0 required Command type */
430 enum {
431 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
432 };
433
434 enum {
435 UTP_SCSI_COMMAND = 0x00000000,
436 UTP_NATIVE_UFS_COMMAND = 0x10000000,
437 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
438 };
439
440 /* UTP Transfer Request Data Direction (DD) */
441 enum utp_data_direction {
442 UTP_NO_DATA_TRANSFER = 0,
443 UTP_HOST_TO_DEVICE = 1,
444 UTP_DEVICE_TO_HOST = 2,
445 };
446
447 /* Overall command status values */
448 enum utp_ocs {
449 OCS_SUCCESS = 0x0,
450 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
451 OCS_INVALID_PRDT_ATTR = 0x2,
452 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
453 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
454 OCS_PEER_COMM_FAILURE = 0x5,
455 OCS_ABORTED = 0x6,
456 OCS_FATAL_ERROR = 0x7,
457 OCS_DEVICE_FATAL_ERROR = 0x8,
458 OCS_INVALID_CRYPTO_CONFIG = 0x9,
459 OCS_GENERAL_CRYPTO_ERROR = 0xA,
460 OCS_INVALID_COMMAND_STATUS = 0x0F,
461 };
462
463 enum {
464 MASK_OCS = 0x0F,
465 };
466
467 /* The maximum length of the data byte count field in the PRDT is 256KB */
468 #define PRDT_DATA_BYTE_COUNT_MAX SZ_256K
469 /* The granularity of the data byte count field in the PRDT is 32-bit */
470 #define PRDT_DATA_BYTE_COUNT_PAD 4
471
472 /**
473 * struct ufshcd_sg_entry - UFSHCI PRD Entry
474 * @addr: Physical address; DW-0 and DW-1.
475 * @reserved: Reserved for future use DW-2
476 * @size: size of physical segment DW-3
477 */
478 struct ufshcd_sg_entry {
479 __le64 addr;
480 __le32 reserved;
481 __le32 size;
482 /*
483 * followed by variant-specific fields if
484 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.
485 */
486 };
487
488 /**
489 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
490 * @command_upiu: Command UPIU Frame address
491 * @response_upiu: Response UPIU Frame address
492 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct
493 * ufshcd_sg_entry's. Variant-specific fields may be present after each.
494 */
495 struct utp_transfer_cmd_desc {
496 u8 command_upiu[ALIGNED_UPIU_SIZE];
497 u8 response_upiu[ALIGNED_UPIU_SIZE];
498 u8 prd_table[];
499 };
500
501 /**
502 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
503 */
504 struct request_desc_header {
505 u8 cci;
506 u8 ehs_length;
507 #if defined(__BIG_ENDIAN)
508 u8 enable_crypto:1;
509 u8 reserved2:7;
510
511 u8 command_type:4;
512 u8 reserved1:1;
513 u8 data_direction:2;
514 u8 interrupt:1;
515 #elif defined(__LITTLE_ENDIAN)
516 u8 reserved2:7;
517 u8 enable_crypto:1;
518
519 u8 interrupt:1;
520 u8 data_direction:2;
521 u8 reserved1:1;
522 u8 command_type:4;
523 #else
524 #error
525 #endif
526
527 __le32 dunl;
528 u8 ocs;
529 u8 cds;
530 __le16 ldbc;
531 __le32 dunu;
532 };
533
534 static_assert(sizeof(struct request_desc_header) == 16);
535
536 /**
537 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
538 * @header: UTRD header DW-0 to DW-3
539 * @command_desc_base_addr: UCD base address DW 4-5
540 * @response_upiu_length: response UPIU length DW-6
541 * @response_upiu_offset: response UPIU offset DW-6
542 * @prd_table_length: Physical region descriptor length DW-7
543 * @prd_table_offset: Physical region descriptor offset DW-7
544 */
545 struct utp_transfer_req_desc {
546
547 /* DW 0-3 */
548 struct request_desc_header header;
549
550 /* DW 4-5*/
551 __le64 command_desc_base_addr;
552
553 /* DW 6 */
554 __le16 response_upiu_length;
555 __le16 response_upiu_offset;
556
557 /* DW 7 */
558 __le16 prd_table_length;
559 __le16 prd_table_offset;
560 };
561
562 /* MCQ Completion Queue Entry */
563 struct cq_entry {
564 /* DW 0-1 */
565 __le64 command_desc_base_addr;
566
567 /* DW 2 */
568 __le16 response_upiu_length;
569 __le16 response_upiu_offset;
570
571 /* DW 3 */
572 __le16 prd_table_length;
573 __le16 prd_table_offset;
574
575 /* DW 4 */
576 u8 overall_status;
577 u8 extended_error_code;
578 __le16 reserved_1;
579
580 /* DW 5 */
581 u8 task_tag;
582 u8 lun;
583 #if defined(__BIG_ENDIAN)
584 u8 ext_iid:4;
585 u8 iid:4;
586 #elif defined(__LITTLE_ENDIAN)
587 u8 iid:4;
588 u8 ext_iid:4;
589 #else
590 #error
591 #endif
592 u8 reserved_2;
593
594 /* DW 6-7 */
595 __le32 reserved_3[2];
596 };
597
598 static_assert(sizeof(struct cq_entry) == 32);
599
600 /*
601 * UTMRD structure.
602 */
603 struct utp_task_req_desc {
604 /* DW 0-3 */
605 struct request_desc_header header;
606
607 /* DW 4-11 - Task request UPIU structure */
608 struct {
609 struct utp_upiu_header req_header;
610 __be32 input_param1;
611 __be32 input_param2;
612 __be32 input_param3;
613 __be32 __reserved1[2];
614 } upiu_req;
615
616 /* DW 12-19 - Task Management Response UPIU structure */
617 struct {
618 struct utp_upiu_header rsp_header;
619 __be32 output_param1;
620 __be32 output_param2;
621 __be32 __reserved2[3];
622 } upiu_rsp;
623 };
624
625 #endif /* End of Header */
626