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Searched refs:DIV_ROUND_UP_ULL (Results 1 – 25 of 145) sorted by relevance

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/linux/drivers/clk/rockchip/
H A Dclk-half-divider.c32 return DIV_ROUND_UP_ULL(((u64)parent_rate * 2), val); in clk_half_divider_recalc_rate()
50 bestdiv = DIV_ROUND_UP_ULL(((u64)parent_rate * 2), rate); in clk_half_divider_bestdiv()
77 now = DIV_ROUND_UP_ULL(((u64)parent_rate * 2), in clk_half_divider_bestdiv()
105 req->rate = DIV_ROUND_UP_ULL(((u64)req->best_parent_rate * 2), div * 2 + 3); in clk_half_divider_determine_rate()
118 value = DIV_ROUND_UP_ULL(((u64)parent_rate * 2), rate); in clk_half_divider_set_rate()
/linux/drivers/clk/zynqmp/
H A Ddivider.c56 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in zynqmp_divider_get_val()
62 up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); in zynqmp_divider_get_val()
63 down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); in zynqmp_divider_get_val()
110 return DIV_ROUND_UP_ULL(parent_rate, value); in zynqmp_clk_divider_recalc_rate()
146 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, bestdiv); in zynqmp_clk_divider_determine_rate()
/linux/drivers/gpu/drm/mcde/
H A Dmcde_clk_div.c60 div_rate = DIV_ROUND_UP_ULL(this_prate, div); in mcde_clk_div_choose_div()
80 req->rate = DIV_ROUND_UP_ULL(req->best_parent_rate, div); in mcde_clk_div_determine_rate()
99 return DIV_ROUND_UP_ULL(prate, 2); in mcde_clk_div_recalc_rate()
109 return DIV_ROUND_UP_ULL(prate, div); in mcde_clk_div_recalc_rate()
/linux/drivers/clk/
H A Dclk-divider.c151 return DIV_ROUND_UP_ULL((u64)parent_rate, div); in divider_recalc_rate()
229 int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_up()
246 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in _div_round_closest()
257 up_rate = DIV_ROUND_UP_ULL((u64)parent_rate, up); in _div_round_closest()
258 down_rate = DIV_ROUND_UP_ULL((u64)parent_rate, down); in _div_round_closest()
336 now = DIV_ROUND_UP_ULL((u64)parent_rate, i); in clk_divider_bestdiv()
361 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); in divider_determine_rate()
384 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); in divider_ro_determine_rate()
461 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate); in divider_get_val()
/linux/drivers/pwm/
H A Dpwm-imx27.c141 state->period = DIV_ROUND_UP_ULL(tmp, pwm_clk); in pwm_imx27_get_state()
153 state->duty_cycle = DIV_ROUND_UP_ULL(tmp, pwm_clk); in pwm_imx27_get_state()
190 period_ms = DIV_ROUND_UP_ULL(pwm->state.period, in pwm_imx27_wait_fifo_slot()
253 tmp = DIV_ROUND_UP_ULL(tmp, clkrate); in pwm_imx27_apply()
254 period_us = DIV_ROUND_UP_ULL(tmp, 1000); in pwm_imx27_apply()
H A Dpwm-keembay.c112 state->duty_cycle = DIV_ROUND_UP_ULL(high, clk_rate); in keembay_pwm_get_state()
113 state->period = DIV_ROUND_UP_ULL(high + low, clk_rate); in keembay_pwm_get_state()
H A Dpwm-sun4i.c129 state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); in sun4i_pwm_get_state()
130 state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); in sun4i_pwm_get_state()
300 delay_us = DIV_ROUND_UP_ULL(cstate.period, NSEC_PER_USEC); in sun4i_pwm_apply()
H A Dpwm-sophgo-sg2042.c136 state->period = DIV_ROUND_UP_ULL((u64)period_ticks * NSEC_PER_SEC, ddata->clk_rate_hz); in pwm_sg2042_get_state()
137 state->duty_cycle = DIV_ROUND_UP_ULL((u64)hlperiod_ticks * NSEC_PER_SEC, ddata->clk_rate_hz); in pwm_sg2042_get_state()
H A Dpwm-sifive.c121 ddata->real_period = DIV_ROUND_UP_ULL(num, rate); in pwm_sifive_update_clock()
146 state->duty_cycle = DIV_ROUND_UP_ULL((u64)duty * ddata->real_period, in pwm_sifive_get_state()
H A Dpwm-mediatek.c250 DIV_ROUND_UP_ULL((u64)(cnt_period + 1) * NSEC_PER_SEC << clkdiv, clk_rate), in pwm_mediatek_round_waveform_fromhw()
252 DIV_ROUND_UP_ULL((u64)(cnt_duty + 1) * NSEC_PER_SEC << clkdiv, clk_rate), in pwm_mediatek_round_waveform_fromhw()
266 DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate), in pwm_mediatek_round_waveform_fromhw()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_fixed.h80 tmp = DIV_ROUND_UP_ULL(tmp, 1 << 16); in mul_round_up_u32_fixed16()
102 tmp = DIV_ROUND_UP_ULL(tmp, d); in div_fixed16()
112 tmp = DIV_ROUND_UP_ULL(tmp, d.val); in div_round_up_u32_fixed16()
H A Dskl_prefill.c24 return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, usecs << 16), in prefill_usecs_to_lines()
69 return DIV_ROUND_UP_ULL(mul_u32_u32(value, factor), 0x10000); in prefill_adjust()
/linux/drivers/spi/
H A Dspi-offload-trigger-pwm.c51 wf.period_length_ns = DIV_ROUND_UP_ULL(NSEC_PER_SEC, periodic->frequency_hz); in spi_offload_trigger_pwm_validate()
60 periodic->frequency_hz = DIV_ROUND_UP_ULL(NSEC_PER_SEC, wf.period_length_ns); in spi_offload_trigger_pwm_validate()
79 wf.period_length_ns = DIV_ROUND_UP_ULL(NSEC_PER_SEC, periodic->frequency_hz); in spi_offload_trigger_pwm_enable()
/linux/drivers/clk/meson/
H A Dsclk-div.c82 now = DIV_ROUND_UP_ULL((u64)parent_now, i); in sclk_div_bestdiv()
107 req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, div); in sclk_div_determine_rate()
188 return DIV_ROUND_UP_ULL((u64)prate, sclk->cached_div); in sclk_div_recalc_rate()
H A Dclk-mpll.c40 return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); in rate_from_params()
57 *sdm = DIV_ROUND_UP_ULL(frac, requested_rate); in params_from_rate()
H A Dvid-pll-div.c89 return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider); in meson_vid_pll_div_recalc_rate()
/linux/include/linux/
H A Dmath.h54 #define DIV_ROUND_UP_ULL(ll, d) \ macro
58 # define DIV_ROUND_UP_SECTOR_T(ll,d) DIV_ROUND_UP_ULL(ll, d)
/linux/drivers/i2c/busses/
H A Di2c-hisi.c88 DIV_ROUND_UP_ULL((clk_rate_khz) * (ns), NSEC_PER_MSEC)
397 total_cnt = DIV_ROUND_UP_ULL(ctlr->clk_rate_khz * HZ_PER_KHZ, ctlr->t.bus_freq_hz); in hisi_i2c_set_scl()
399 t_scl_hcnt = DIV_ROUND_UP_ULL(total_cnt * divide, divisor); in hisi_i2c_set_scl()
496 ctlr->clk_rate_khz = DIV_ROUND_UP_ULL(clk_rate_hz, HZ_PER_KHZ); in hisi_i2c_probe()
/linux/drivers/gpu/drm/i915/
H A Di915_scatterlist.c100 if (WARN_ON(overflows_type(DIV_ROUND_UP_ULL(node->size, segment_pages), in i915_rsgt_from_mm_node()
106 if (sg_alloc_table(st, DIV_ROUND_UP_ULL(node->size, segment_pages), in i915_rsgt_from_mm_node()
/linux/drivers/clk/ti/
H A Dfapll.c350 return DIV_ROUND_UP_ULL(rate, synth_div_m); in ti_fapll_synth_recalc_rate()
373 post_div_m = DIV_ROUND_UP_ULL((u64)parent_rate * SYNTH_PHASE_K, rate); in ti_fapll_synth_set_frac_rate()
381 synth_int_div = DIV_ROUND_UP_ULL((u64)parent_rate * in ti_fapll_synth_set_frac_rate()
431 r = DIV_ROUND_UP_ULL(r, SYNTH_MAX_INT_DIV * SYNTH_MAX_DIV_M); in ti_fapll_synth_determine_rate()
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi5_core.c52 v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000); in hdmi5_core_ddc_init()
59 v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000); in hdmi5_core_ddc_init()
66 v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000); in hdmi5_core_ddc_init()
73 v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000); in hdmi5_core_ddc_init()
80 v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000); in hdmi5_core_ddc_init()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi5_core.c65 v = DIV_ROUND_UP_ULL(ss_scl_high * sfr, 1000000); in hdmi_core_ddc_init()
72 v = DIV_ROUND_UP_ULL(ss_scl_low * sfr, 1000000); in hdmi_core_ddc_init()
79 v = DIV_ROUND_UP_ULL(fs_scl_high * sfr, 1000000); in hdmi_core_ddc_init()
86 v = DIV_ROUND_UP_ULL(fs_scl_low * sfr, 1000000); in hdmi_core_ddc_init()
93 v = DIV_ROUND_UP_ULL(sda_hold * sfr, 1000000); in hdmi_core_ddc_init()
/linux/net/ceph/
H A Dstriper.c231 *num_file_extents = DIV_ROUND_UP_ULL(objoff + objlen, l->stripe_unit) - in ceph_extent_to_file()
274 DIV_ROUND_UP_ULL(remainder_bytes, l->stripe_unit); in ceph_get_num_objects()
/linux/arch/arm/mach-omap2/
H A Dtimer.c155 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); in realtime_counter_init()
/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Ddm.c147 u32 num_blocks = DIV_ROUND_UP_ULL(length, MLX5_SW_ICM_BLOCK_SIZE(dev)); in mlx5_dm_sw_icm_alloc()
250 u32 num_blocks = DIV_ROUND_UP_ULL(length, MLX5_SW_ICM_BLOCK_SIZE(dev)); in mlx5_dm_sw_icm_dealloc()

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