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Searched refs:DCCG_GATE_DISABLE_CNTL2 (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.h68 SR(DCCG_GATE_DISABLE_CNTL2),\
148 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\
149 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\
150 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\
151 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\
152 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\
H A Ddcn31_dccg.c459 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
466 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
476 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
483 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
493 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
500 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
510 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
517 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
527 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
534 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg31_set_physymclk()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/
H A Ddcn314_dccg.h74 SR(DCCG_GATE_DISABLE_CNTL2),\
193 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_GATE_DISABLE, mask_sh),\
194 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_GATE_DISABLE, mask_sh),\
195 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_GATE_DISABLE, mask_sh),\
196 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_GATE_DISABLE, mask_sh),\
197 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_GATE_DISABLE, mask_sh),\
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.c246 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
250 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
254 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
258 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
262 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_physymclk_rcg()
283 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_symclk_fe_rcg()
289 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_symclk_fe_rcg()
295 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_symclk_fe_rcg()
301 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_symclk_fe_rcg()
307 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg35_set_symclk_fe_rcg()
[all …]
H A Ddcn35_dccg.h155 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\
156 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
157 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
158 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
159 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
198 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
H A Ddcn401_dccg.c284 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg401_set_physymclk()
291 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg401_set_physymclk()
301 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg401_set_physymclk()
308 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg401_set_physymclk()
318 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg401_set_physymclk()
325 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg401_set_physymclk()
335 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg401_set_physymclk()
342 REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, in dccg401_set_physymclk()
H A Ddcn401_dccg.h104 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, mask_sh),\
105 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
106 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
107 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh),\
128 DCCG_SF(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c605 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
606 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
607 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
608 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
609 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
610 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
611 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
612 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
613 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
614 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
[all …]
H A Ddcn36_resource.h30 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c618 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
619 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
620 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
621 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
622 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
623 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
624 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
625 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
626 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
627 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
[all …]
H A Ddcn35_resource.h169 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c598 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, mask_sh), \
599 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_FE_GATE_DISABLE, mask_sh), \
600 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_FE_GATE_DISABLE, mask_sh), \
601 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_FE_GATE_DISABLE, mask_sh), \
602 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKE_FE_GATE_DISABLE, mask_sh), \
603 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, mask_sh), \
604 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, mask_sh), \
605 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKB_GATE_DISABLE, mask_sh), \
606 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKC_GATE_DISABLE, mask_sh), \
607 HWS_SF(, DCCG_GATE_DISABLE_CNTL2, SYMCLKD_GATE_DISABLE, mask_sh), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c170 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); in dccg2_allow_clock_gating()
173 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF); in dccg2_allow_clock_gating()
H A Ddcn20_dccg.h45 SR(DCCG_GATE_DISABLE_CNTL2)
419 uint32_t DCCG_GATE_DISABLE_CNTL2; \
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn301/
H A Ddcn301_dccg.h43 SR(DCCG_GATE_DISABLE_CNTL2)
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.h199 SR(DCCG_GATE_DISABLE_CNTL2), \
424 SR(DCCG_GATE_DISABLE_CNTL2), \
636 uint32_t DCCG_GATE_DISABLE_CNTL2; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c681 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn314/
H A Ddcn314_resource.c694 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn315/
H A Ddcn315_resource.c686 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c687 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c534 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c513 SR(DCCG_GATE_DISABLE_CNTL2), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c538 SR(DCCG_GATE_DISABLE_CNTL2), \