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/linux/arch/x86/events/zhaoxin/
H A Dcore.c52 [C(L1D)] = {
53 [C(OP_READ)] = {
54 [C(RESULT_ACCESS)] = 0x0042,
55 [C(RESULT_MISS)] = 0x0538,
57 [C(OP_WRITE)] = {
58 [C(RESULT_ACCESS)] = 0x0043,
59 [C(RESULT_MISS)] = 0x0562,
61 [C(OP_PREFETCH)] = {
62 [C(RESULT_ACCESS)] = -1,
63 [C(RESULT_MISS)] = -1,
[all …]
/linux/arch/sh/kernel/cpu/sh4/
H A Dperf_event.c84 #define C(x) PERF_COUNT_HW_CACHE_##x macro
91 [ C(L1D) ] = {
92 [ C(OP_READ) ] = {
93 [ C(RESULT_ACCESS) ] = 0x0001,
94 [ C(RESULT_MISS) ] = 0x0004,
96 [ C(OP_WRITE) ] = {
97 [ C(RESULT_ACCESS) ] = 0x0002,
98 [ C(RESULT_MISS) ] = 0x0005,
100 [ C(OP_PREFETCH) ] = {
101 [ C(RESULT_ACCESS) ] = 0,
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dperf_event.c109 #define C(x) PERF_COUNT_HW_CACHE_##x macro
116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
118 [ C(RESULT_ACCESS) ] = 0x0031,
119 [ C(RESULT_MISS) ] = 0x0032,
121 [ C(OP_WRITE) ] = {
122 [ C(RESULT_ACCESS) ] = 0x0039,
123 [ C(RESULT_MISS) ] = 0x003a,
125 [ C(OP_PREFETCH) ] = {
126 [ C(RESULT_ACCESS) ] = 0,
[all …]
/linux/arch/powerpc/perf/
H A Dpower10-pmu.c351 #define C(x) PERF_COUNT_HW_CACHE_##x macro
358 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
359 [C(L1D)] = {
360 [C(OP_READ)] = {
361 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
362 [C(RESULT_MISS)] = PM_LD_MISS_L1,
364 [C(OP_WRITE)] = {
365 [C(RESULT_ACCESS)] = 0,
366 [C(RESULT_MISS)] = PM_ST_MISS_L1,
368 [C(OP_PREFETCH)] = {
[all …]
H A Dgeneric-compat-pmu.c178 #define C(x) PERF_COUNT_HW_CACHE_##x macro
185 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
186 [ C(L1D) ] = {
187 [ C(OP_READ) ] = {
188 [ C(RESULT_ACCESS) ] = 0,
189 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
191 [ C(OP_WRITE) ] = {
192 [ C(RESULT_ACCESS) ] = 0,
193 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
195 [ C(OP_PREFETCH) ] = {
[all …]
H A Dpower8-pmu.c259 #define C(x) PERF_COUNT_HW_CACHE_##x macro
266 static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
267 [ C(L1D) ] = {
268 [ C(OP_READ) ] = {
269 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
270 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
272 [ C(OP_WRITE) ] = {
273 [ C(RESULT_ACCESS) ] = 0,
274 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
276 [ C(OP_PREFETCH) ] = {
[all …]
H A Dpower9-pmu.c330 #define C(x) PERF_COUNT_HW_CACHE_##x macro
337 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
338 [ C(L1D) ] = {
339 [ C(OP_READ) ] = {
340 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
341 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
343 [ C(OP_WRITE) ] = {
344 [ C(RESULT_ACCESS) ] = 0,
345 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
347 [ C(OP_PREFETCH) ] = {
[all …]
H A De6500-pmu.c28 #define C(x) PERF_COUNT_HW_CACHE_##x macro
35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36 [C(L1D)] = {
38 [C(OP_READ)] = { 27, 222 },
39 [C(OP_WRITE)] = { 28, 223 },
40 [C(OP_PREFETCH)] = { 29, 0 },
42 [C(L1I)] = {
44 [C(OP_READ)] = { 2, 254 },
45 [C(OP_WRITE)] = { -1, -1 },
46 [C(OP_PREFETCH)] = { 37, 0 },
[all …]
H A De500-pmu.c27 #define C(x) PERF_COUNT_HW_CACHE_##x macro
34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
39 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
42 [C(OP_PREFETCH)] = { 29, 0 },
44 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
/linux/drivers/perf/
H A Darm_v7_pmu.c177 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
178 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
179 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
180 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
182 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
183 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
185 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
186 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
187 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
188 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
[all …]
H A Driscv_pmu_sbi.c157 #define C(x) PERF_COUNT_HW_CACHE_##x macro
161 [C(L1D)] = {
162 [C(OP_READ)] = {
163 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
164 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
165 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
166 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
168 [C(OP_WRITE)] = {
169 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
170 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
[all …]
H A Darm_pmuv3.c62 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
63 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
65 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
66 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
68 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
69 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
71 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
72 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
74 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
75 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
[all …]
/linux/arch/sparc/kernel/
H A Dperf_event.c147 #define C(x) PERF_COUNT_HW_CACHE_##x macro
221 [C(L1D)] = {
222 [C(OP_READ)] = {
223 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
224 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
226 [C(OP_WRITE)] = {
227 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
228 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
230 [C(OP_PREFETCH)] = {
231 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
[all …]
/linux/rust/kernel/time/
H A Dhrtimer.rs86 #[repr(C)]
522 impl<C: ClockSource> HrTimerExpires for Instant<C> {
525 Instant::<C>::as_nanos(self) in as_nanos()
541 impl<C: ClockSource> Sealed for super::AbsoluteMode<C> {}
542 impl<C: ClockSource> Sealed for super::RelativeMode<C> {}
543 impl<C: ClockSource> Sealed for super::AbsolutePinnedMode<C> {}
544 impl<C: ClockSource> Sealed for super::RelativePinnedMode<C> {}
545 impl<C: ClockSource> Sealed for super::AbsoluteSoftMode<C> {}
546 impl<C: ClockSource> Sealed for super::RelativeSoftMode<C> {}
547 impl<C: ClockSource> Sealed for super::AbsolutePinnedSoftMode<C> {}
[all …]
/linux/arch/x86/events/intel/
H A Dknc.c27 [ C(L1D) ] = {
28 [ C(OP_READ) ] = {
33 [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
35 [ C(RESULT_MISS) ] = 0x0003, /* DATA_READ_MISS */
37 [ C(OP_WRITE) ] = {
38 [ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */
39 [ C(RESULT_MISS) ] = 0x0004, /* DATA_WRITE_MISS */
41 [ C(OP_PREFETCH) ] = {
42 [ C(RESULT_ACCESS) ] = 0x0011, /* L1_DATA_PF1 */
43 [ C(RESULT_MISS) ] = 0x001c, /* L1_DATA_PF1_MISS */
[all …]
H A Dcore.c635 [ C(L1D ) ] = {
636 [ C(OP_READ) ] = {
637 [ C(RESULT_ACCESS) ] = 0x81d0,
638 [ C(RESULT_MISS) ] = 0xe124,
640 [ C(OP_WRITE) ] = {
641 [ C(RESULT_ACCESS) ] = 0x82d0,
644 [ C(L1I ) ] = {
645 [ C(OP_READ) ] = {
646 [ C(RESULT_MISS) ] = 0xe424,
648 [ C(OP_WRITE) ] = {
[all …]
/linux/tools/testing/selftests/bpf/progs/
H A Dtest_verif_scale2.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dtest_verif_scale1.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dtest_verif_scale3.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
H A Dcore_kern.c85 #define C do { \ in balancer_ingress() macro
99 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
/linux/arch/mips/kernel/
H A Dperf_event_mipsxx.c74 #define C(x) PERF_COUNT_HW_CACHE_##x macro
1009 [C(L1D)] = {
1016 [C(OP_READ)] = {
1017 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1018 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1020 [C(OP_WRITE)] = {
1021 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1022 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1025 [C(L1I)] = {
1026 [C(OP_READ)] = {
[all …]
/linux/arch/x86/events/amd/
H A Dcore.c33 [ C(L1D) ] = {
34 [ C(OP_READ) ] = {
35 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
36 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
38 [ C(OP_WRITE) ] = {
39 [ C(RESULT_ACCESS) ] = 0,
40 [ C(RESULT_MISS) ] = 0,
42 [ C(OP_PREFETCH) ] = {
43 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
44 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
[all …]
/linux/kernel/trace/
H A Dtrace_probe.h485 C(FILE_NOT_FOUND, "Failed to find the given file"), \
486 C(NO_REGULAR_FILE, "Not a regular file"), \
487 C(BAD_REFCNT, "Invalid reference counter offset"), \
488 C(REFCNT_OPEN_BRACE, "Reference counter brace is not closed"), \
489 C(BAD_REFCNT_SUFFIX, "Reference counter has wrong suffix"), \
490 C(BAD_UPROBE_OFFS, "Invalid uprobe offset"), \
491 C(BAD_MAXACT_TYPE, "Maxactive is only for function exit"), \
492 C(BAD_MAXACT, "Invalid maxactive number"), \
493 C(MAXACT_TOO_BIG, "Maxactive is too big"), \
494 C(BAD_PROBE_ADDR, "Invalid probed address or symbol"), \
[all …]
/linux/lib/zstd/common/
H A Dcpu.h98 #define C(name, bit) X(name, f1c, bit) macro
99 C(sse3, 0)
100 C(pclmuldq, 1)
101 C(dtes64, 2)
102 C(monitor, 3)
103 C(dscpl, 4)
104 C(vmx, 5)
105 C(smx, 6)
106 C(eist, 7)
107 C(tm2, 8)
[all …]
/linux/arch/arc/kernel/
H A Dperf_event.c77 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
80 static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
81 [C(L1D)] = {
82 [C(OP_READ)] = {
83 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
84 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
86 [C(OP_WRITE)] = {
87 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
88 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
90 [C(OP_PREFETCH)] = {
[all …]

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