1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIO driver for AMD
4 *
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <Ken.Xue@amd.com>
7 * Wu, Jeff <Jeff.Wu@amd.com>
8 *
9 */
10
11 #include <linux/err.h>
12 #include <linux/bug.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/compiler.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/log2.h>
20 #include <linux/io.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/slab.h>
23 #include <linux/platform_device.h>
24 #include <linux/mutex.h>
25 #include <linux/acpi.h>
26 #include <linux/seq_file.h>
27 #include <linux/interrupt.h>
28 #include <linux/list.h>
29 #include <linux/bitops.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/string_choices.h>
34 #include <linux/suspend.h>
35
36 #include "core.h"
37 #include "pinctrl-utils.h"
38 #include "pinctrl-amd.h"
39
40 #ifdef CONFIG_SUSPEND
41 static struct amd_gpio *pinctrl_dev;
42 #endif
43
amd_gpio_get_direction(struct gpio_chip * gc,unsigned offset)44 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
45 {
46 unsigned long flags;
47 u32 pin_reg;
48 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
49
50 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
51 pin_reg = readl(gpio_dev->base + offset * 4);
52 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
53
54 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
55 return GPIO_LINE_DIRECTION_OUT;
56
57 return GPIO_LINE_DIRECTION_IN;
58 }
59
amd_gpio_direction_input(struct gpio_chip * gc,unsigned offset)60 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
61 {
62 unsigned long flags;
63 u32 pin_reg;
64 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
65
66 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
67 pin_reg = readl(gpio_dev->base + offset * 4);
68 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
69 writel(pin_reg, gpio_dev->base + offset * 4);
70 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
71
72 return 0;
73 }
74
amd_gpio_direction_output(struct gpio_chip * gc,unsigned offset,int value)75 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
76 int value)
77 {
78 u32 pin_reg;
79 unsigned long flags;
80 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
81
82 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
83 pin_reg = readl(gpio_dev->base + offset * 4);
84 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
85 if (value)
86 pin_reg |= BIT(OUTPUT_VALUE_OFF);
87 else
88 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
89 writel(pin_reg, gpio_dev->base + offset * 4);
90 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
91
92 return 0;
93 }
94
amd_gpio_get_value(struct gpio_chip * gc,unsigned offset)95 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
96 {
97 u32 pin_reg;
98 unsigned long flags;
99 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
100
101 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
102 pin_reg = readl(gpio_dev->base + offset * 4);
103 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
104
105 return !!(pin_reg & BIT(PIN_STS_OFF));
106 }
107
amd_gpio_set_value(struct gpio_chip * gc,unsigned int offset,int value)108 static int amd_gpio_set_value(struct gpio_chip *gc, unsigned int offset,
109 int value)
110 {
111 u32 pin_reg;
112 unsigned long flags;
113 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
114
115 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
116 pin_reg = readl(gpio_dev->base + offset * 4);
117 if (value)
118 pin_reg |= BIT(OUTPUT_VALUE_OFF);
119 else
120 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
121 writel(pin_reg, gpio_dev->base + offset * 4);
122 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
123
124 return 0;
125 }
126
amd_gpio_set_debounce(struct amd_gpio * gpio_dev,unsigned int offset,unsigned int debounce)127 static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
128 unsigned int debounce)
129 {
130 u32 time;
131 u32 pin_reg;
132 int ret = 0;
133
134 /* Use special handling for Pin0 debounce */
135 if (offset == 0) {
136 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
137 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
138 debounce = 0;
139 }
140
141 pin_reg = readl(gpio_dev->base + offset * 4);
142
143 if (debounce) {
144 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
145 pin_reg &= ~DB_TMR_OUT_MASK;
146 /*
147 Debounce Debounce Timer Max
148 TmrLarge TmrOutUnit Unit Debounce
149 Time
150 0 0 61 usec (2 RtcClk) 976 usec
151 0 1 244 usec (8 RtcClk) 3.9 msec
152 1 0 15.6 msec (512 RtcClk) 250 msec
153 1 1 62.5 msec (2048 RtcClk) 1 sec
154 */
155
156 if (debounce < 61) {
157 pin_reg |= 1;
158 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
159 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
160 } else if (debounce < 976) {
161 time = debounce / 61;
162 pin_reg |= time & DB_TMR_OUT_MASK;
163 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
164 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
165 } else if (debounce < 3900) {
166 time = debounce / 244;
167 pin_reg |= time & DB_TMR_OUT_MASK;
168 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
169 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
170 } else if (debounce < 250000) {
171 time = debounce / 15625;
172 pin_reg |= time & DB_TMR_OUT_MASK;
173 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
174 pin_reg |= BIT(DB_TMR_LARGE_OFF);
175 } else if (debounce < 1000000) {
176 time = debounce / 62500;
177 pin_reg |= time & DB_TMR_OUT_MASK;
178 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
179 pin_reg |= BIT(DB_TMR_LARGE_OFF);
180 } else {
181 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
182 ret = -EINVAL;
183 }
184 } else {
185 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
186 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
187 pin_reg &= ~DB_TMR_OUT_MASK;
188 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
189 }
190 writel(pin_reg, gpio_dev->base + offset * 4);
191
192 return ret;
193 }
194
195 #ifdef CONFIG_DEBUG_FS
amd_gpio_dbg_show(struct seq_file * s,struct gpio_chip * gc)196 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
197 {
198 u32 pin_reg;
199 u32 db_cntrl;
200 unsigned long flags;
201 unsigned int bank, i, pin_num;
202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
203
204 bool tmr_out_unit;
205 bool tmr_large;
206
207 char *level_trig;
208 char *active_level;
209 char *interrupt_mask;
210 char *wake_cntrl0;
211 char *wake_cntrl1;
212 char *wake_cntrl2;
213 char *pin_sts;
214 char *interrupt_sts;
215 char *wake_sts;
216 char *orientation;
217 char debounce_value[40];
218 char *debounce_enable;
219 char *wake_cntrlz;
220
221 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
222 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
223 unsigned int time = 0;
224 unsigned int unit = 0;
225
226 switch (bank) {
227 case 0:
228 i = 0;
229 pin_num = AMD_GPIO_PINS_BANK0;
230 break;
231 case 1:
232 i = 64;
233 pin_num = AMD_GPIO_PINS_BANK1 + i;
234 break;
235 case 2:
236 i = 128;
237 pin_num = AMD_GPIO_PINS_BANK2 + i;
238 break;
239 case 3:
240 i = 192;
241 pin_num = AMD_GPIO_PINS_BANK3 + i;
242 break;
243 default:
244 /* Illegal bank number, ignore */
245 continue;
246 }
247 seq_printf(s, "GPIO bank%d\n", bank);
248 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n");
249 for (; i < pin_num; i++) {
250 seq_printf(s, "#%d\t", i);
251 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
252 pin_reg = readl(gpio_dev->base + i * 4);
253 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
254
255 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
256 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
257 ACTIVE_LEVEL_MASK;
258
259 if (level == ACTIVE_LEVEL_HIGH)
260 active_level = "↑";
261 else if (level == ACTIVE_LEVEL_LOW)
262 active_level = "↓";
263 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
264 level == ACTIVE_LEVEL_BOTH)
265 active_level = "b";
266 else
267 active_level = "?";
268
269 if (pin_reg & BIT(LEVEL_TRIG_OFF))
270 level_trig = "level";
271 else
272 level_trig = " edge";
273
274 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
275 interrupt_mask = "��";
276 else
277 interrupt_mask = "��";
278
279 if (pin_reg & BIT(INTERRUPT_STS_OFF))
280 interrupt_sts = "��";
281 else
282 interrupt_sts = " ";
283
284 seq_printf(s, "%s %s| %s| %s|",
285 interrupt_sts,
286 interrupt_mask,
287 active_level,
288 level_trig);
289 } else
290 seq_puts(s, " ∅| | |");
291
292 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
293 wake_cntrl0 = "⏰";
294 else
295 wake_cntrl0 = " ";
296 seq_printf(s, " %s| ", wake_cntrl0);
297
298 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
299 wake_cntrl1 = "⏰";
300 else
301 wake_cntrl1 = " ";
302 seq_printf(s, "%s|", wake_cntrl1);
303
304 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
305 wake_cntrl2 = "⏰";
306 else
307 wake_cntrl2 = " ";
308 seq_printf(s, " %s|", wake_cntrl2);
309
310 if (pin_reg & BIT(WAKECNTRL_Z_OFF))
311 wake_cntrlz = "⏰";
312 else
313 wake_cntrlz = " ";
314 seq_printf(s, "%s|", wake_cntrlz);
315
316 if (pin_reg & BIT(WAKE_STS_OFF))
317 wake_sts = "��";
318 else
319 wake_sts = " ";
320 seq_printf(s, " %s|", wake_sts);
321
322 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
323 seq_puts(s, " ↑ |");
324 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) {
325 seq_puts(s, " ↓ |");
326 } else {
327 seq_puts(s, " |");
328 }
329
330 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
331 pin_sts = "output";
332 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
333 orientation = "↑";
334 else
335 orientation = "↓";
336 } else {
337 pin_sts = "input ";
338 if (pin_reg & BIT(PIN_STS_OFF))
339 orientation = "↑";
340 else
341 orientation = "↓";
342 }
343 seq_printf(s, "%s %s|", pin_sts, orientation);
344
345 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
346 if (db_cntrl) {
347 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
348 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
349 time = pin_reg & DB_TMR_OUT_MASK;
350 if (tmr_large) {
351 if (tmr_out_unit)
352 unit = 62500;
353 else
354 unit = 15625;
355 } else {
356 if (tmr_out_unit)
357 unit = 244;
358 else
359 unit = 61;
360 }
361 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
362 debounce_enable = "b";
363 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
364 debounce_enable = "↓";
365 else
366 debounce_enable = "↑";
367 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit);
368 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value);
369 } else {
370 seq_puts(s, " |");
371 }
372 seq_printf(s, "0x%x\n", pin_reg);
373 }
374 }
375 }
376 #else
377 #define amd_gpio_dbg_show NULL
378 #endif
379
amd_gpio_irq_enable(struct irq_data * d)380 static void amd_gpio_irq_enable(struct irq_data *d)
381 {
382 u32 pin_reg;
383 unsigned long flags;
384 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
385 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
386 irq_hw_number_t hwirq = irqd_to_hwirq(d);
387
388 gpiochip_enable_irq(gc, hwirq);
389
390 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
391 pin_reg = readl(gpio_dev->base + hwirq * 4);
392 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
393 pin_reg |= BIT(INTERRUPT_MASK_OFF);
394 writel(pin_reg, gpio_dev->base + hwirq * 4);
395 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
396 }
397
amd_gpio_irq_disable(struct irq_data * d)398 static void amd_gpio_irq_disable(struct irq_data *d)
399 {
400 u32 pin_reg;
401 unsigned long flags;
402 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
403 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
404 irq_hw_number_t hwirq = irqd_to_hwirq(d);
405
406 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
407 pin_reg = readl(gpio_dev->base + hwirq * 4);
408 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
409 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
410 writel(pin_reg, gpio_dev->base + hwirq * 4);
411 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
412
413 gpiochip_disable_irq(gc, hwirq);
414 }
415
amd_gpio_irq_mask(struct irq_data * d)416 static void amd_gpio_irq_mask(struct irq_data *d)
417 {
418 u32 pin_reg;
419 unsigned long flags;
420 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
421 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
422 irq_hw_number_t hwirq = irqd_to_hwirq(d);
423
424 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
425 pin_reg = readl(gpio_dev->base + hwirq * 4);
426 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
427 writel(pin_reg, gpio_dev->base + hwirq * 4);
428 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
429 }
430
amd_gpio_irq_unmask(struct irq_data * d)431 static void amd_gpio_irq_unmask(struct irq_data *d)
432 {
433 u32 pin_reg;
434 unsigned long flags;
435 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
436 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
437 irq_hw_number_t hwirq = irqd_to_hwirq(d);
438
439 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
440 pin_reg = readl(gpio_dev->base + hwirq * 4);
441 pin_reg |= BIT(INTERRUPT_MASK_OFF);
442 writel(pin_reg, gpio_dev->base + hwirq * 4);
443 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
444 }
445
amd_gpio_irq_set_wake(struct irq_data * d,unsigned int on)446 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
447 {
448 u32 pin_reg;
449 unsigned long flags;
450 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
451 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
452 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
453 irq_hw_number_t hwirq = irqd_to_hwirq(d);
454 int err;
455
456 pm_pr_dbg("Setting wake for GPIO %lu to %s\n",
457 hwirq, str_enable_disable(on));
458
459 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
460 pin_reg = readl(gpio_dev->base + hwirq * 4);
461
462 if (on)
463 pin_reg |= wake_mask;
464 else
465 pin_reg &= ~wake_mask;
466
467 writel(pin_reg, gpio_dev->base + hwirq * 4);
468 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
469
470 if (on)
471 err = enable_irq_wake(gpio_dev->irq);
472 else
473 err = disable_irq_wake(gpio_dev->irq);
474
475 if (err)
476 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
477 str_enable_disable(on));
478
479 return 0;
480 }
481
amd_gpio_irq_eoi(struct irq_data * d)482 static void amd_gpio_irq_eoi(struct irq_data *d)
483 {
484 u32 reg;
485 unsigned long flags;
486 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
487 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
488
489 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
490 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
491 reg |= EOI_MASK;
492 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
493 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
494 }
495
amd_gpio_irq_set_type(struct irq_data * d,unsigned int type)496 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
497 {
498 int ret = 0;
499 u32 pin_reg, pin_reg_irq_en, mask;
500 unsigned long flags;
501 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
502 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
503 irq_hw_number_t hwirq = irqd_to_hwirq(d);
504
505 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
506 pin_reg = readl(gpio_dev->base + hwirq * 4);
507
508 switch (type & IRQ_TYPE_SENSE_MASK) {
509 case IRQ_TYPE_EDGE_RISING:
510 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
511 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
512 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
513 irq_set_handler_locked(d, handle_edge_irq);
514 break;
515
516 case IRQ_TYPE_EDGE_FALLING:
517 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
518 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
519 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
520 irq_set_handler_locked(d, handle_edge_irq);
521 break;
522
523 case IRQ_TYPE_EDGE_BOTH:
524 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
525 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
526 pin_reg |= BOTH_EDGES << ACTIVE_LEVEL_OFF;
527 irq_set_handler_locked(d, handle_edge_irq);
528 break;
529
530 case IRQ_TYPE_LEVEL_HIGH:
531 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
532 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
533 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
534 irq_set_handler_locked(d, handle_level_irq);
535 break;
536
537 case IRQ_TYPE_LEVEL_LOW:
538 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
539 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
540 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
541 irq_set_handler_locked(d, handle_level_irq);
542 break;
543
544 case IRQ_TYPE_NONE:
545 break;
546
547 default:
548 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
549 ret = -EINVAL;
550 }
551
552 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
553 /*
554 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
555 * debounce registers of any GPIO will block wake/interrupt status
556 * generation for *all* GPIOs for a length of time that depends on
557 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
558 * INTERRUPT_ENABLE bit will read as 0.
559 *
560 * We temporarily enable irq for the GPIO whose configuration is
561 * changing, and then wait for it to read back as 1 to know when
562 * debounce has settled and then disable the irq again.
563 * We do this polling with the spinlock held to ensure other GPIO
564 * access routines do not read an incorrect value for the irq enable
565 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
566 * spurious irqs, and disable the irq again after polling.
567 */
568 mask = BIT(INTERRUPT_ENABLE_OFF);
569 pin_reg_irq_en = pin_reg;
570 pin_reg_irq_en |= mask;
571 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
572 writel(pin_reg_irq_en, gpio_dev->base + hwirq * 4);
573 while ((readl(gpio_dev->base + hwirq * 4) & mask) != mask)
574 continue;
575 writel(pin_reg, gpio_dev->base + hwirq * 4);
576 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
577
578 return ret;
579 }
580
amd_irq_ack(struct irq_data * d)581 static void amd_irq_ack(struct irq_data *d)
582 {
583 /*
584 * based on HW design,there is no need to ack HW
585 * before handle current irq. But this routine is
586 * necessary for handle_edge_irq
587 */
588 }
589
590 static const struct irq_chip amd_gpio_irqchip = {
591 .name = "amd_gpio",
592 .irq_ack = amd_irq_ack,
593 .irq_enable = amd_gpio_irq_enable,
594 .irq_disable = amd_gpio_irq_disable,
595 .irq_mask = amd_gpio_irq_mask,
596 .irq_unmask = amd_gpio_irq_unmask,
597 .irq_set_wake = amd_gpio_irq_set_wake,
598 .irq_eoi = amd_gpio_irq_eoi,
599 .irq_set_type = amd_gpio_irq_set_type,
600 /*
601 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
602 * also generates an IRQ. We need the IRQ so the irq_handler can clear
603 * the wake event. Otherwise the wake event will never clear and
604 * prevent the system from suspending.
605 */
606 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
607 GPIOCHIP_IRQ_RESOURCE_HELPERS,
608 };
609
610 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
611
do_amd_gpio_irq_handler(int irq,void * dev_id)612 static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
613 {
614 struct amd_gpio *gpio_dev = dev_id;
615 struct gpio_chip *gc = &gpio_dev->gc;
616 unsigned int i, irqnr;
617 unsigned long flags;
618 u32 __iomem *regs;
619 bool ret = false;
620 u32 regval;
621 u64 status, mask;
622
623 /* Read the wake status */
624 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
625 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
626 status <<= 32;
627 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
628 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
629
630 /* Bit 0-45 contain the relevant status bits */
631 status &= (1ULL << 46) - 1;
632 regs = gpio_dev->base;
633 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
634 if (!(status & mask))
635 continue;
636 status &= ~mask;
637
638 /* Each status bit covers four pins */
639 for (i = 0; i < 4; i++) {
640 regval = readl(regs + i);
641
642 if (regval & PIN_IRQ_PENDING)
643 pm_pr_dbg("GPIO %d is active: 0x%x",
644 irqnr + i, regval);
645
646 /* caused wake on resume context for shared IRQ */
647 if (irq < 0 && (regval & BIT(WAKE_STS_OFF)))
648 return true;
649
650 if (!(regval & PIN_IRQ_PENDING) ||
651 !(regval & BIT(INTERRUPT_MASK_OFF)))
652 continue;
653 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i);
654
655 /* Clear interrupt.
656 * We must read the pin register again, in case the
657 * value was changed while executing
658 * generic_handle_domain_irq() above.
659 * If the line is not an irq, disable it in order to
660 * avoid a system hang caused by an interrupt storm.
661 */
662 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
663 regval = readl(regs + i);
664 if (!gpiochip_line_is_irq(gc, irqnr + i)) {
665 regval &= ~BIT(INTERRUPT_MASK_OFF);
666 dev_dbg(&gpio_dev->pdev->dev,
667 "Disabling spurious GPIO IRQ %d\n",
668 irqnr + i);
669 } else {
670 ret = true;
671 }
672 writel(regval, regs + i);
673 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
674 }
675 }
676 /* did not cause wake on resume context for shared IRQ */
677 if (irq < 0)
678 return false;
679
680 /* Signal EOI to the GPIO unit */
681 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
682 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
683 regval |= EOI_MASK;
684 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
685 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
686
687 return ret;
688 }
689
amd_gpio_irq_handler(int irq,void * dev_id)690 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
691 {
692 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
693 }
694
amd_gpio_check_wake(void * dev_id)695 static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
696 {
697 return do_amd_gpio_irq_handler(-1, dev_id);
698 }
699
amd_get_groups_count(struct pinctrl_dev * pctldev)700 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
701 {
702 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
703
704 return gpio_dev->ngroups;
705 }
706
amd_get_group_name(struct pinctrl_dev * pctldev,unsigned group)707 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
708 unsigned group)
709 {
710 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
711
712 return gpio_dev->groups[group].name;
713 }
714
amd_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)715 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
716 unsigned group,
717 const unsigned **pins,
718 unsigned *num_pins)
719 {
720 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
721
722 *pins = gpio_dev->groups[group].pins;
723 *num_pins = gpio_dev->groups[group].npins;
724 return 0;
725 }
726
727 static const struct pinctrl_ops amd_pinctrl_ops = {
728 .get_groups_count = amd_get_groups_count,
729 .get_group_name = amd_get_group_name,
730 .get_group_pins = amd_get_group_pins,
731 #ifdef CONFIG_OF
732 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
733 .dt_free_map = pinctrl_utils_free_map,
734 #endif
735 };
736
amd_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)737 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
738 unsigned int pin,
739 unsigned long *config)
740 {
741 u32 pin_reg;
742 unsigned arg;
743 unsigned long flags;
744 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
745 enum pin_config_param param = pinconf_to_config_param(*config);
746
747 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
748 pin_reg = readl(gpio_dev->base + pin*4);
749 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
750 switch (param) {
751 case PIN_CONFIG_INPUT_DEBOUNCE:
752 arg = pin_reg & DB_TMR_OUT_MASK;
753 break;
754
755 case PIN_CONFIG_BIAS_PULL_DOWN:
756 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
757 break;
758
759 case PIN_CONFIG_BIAS_PULL_UP:
760 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0);
761 break;
762
763 case PIN_CONFIG_DRIVE_STRENGTH:
764 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
765 break;
766
767 default:
768 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
769 param);
770 return -ENOTSUPP;
771 }
772
773 *config = pinconf_to_config_packed(param, arg);
774
775 return 0;
776 }
777
amd_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)778 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
779 unsigned long *configs, unsigned int num_configs)
780 {
781 int i;
782 u32 arg;
783 int ret = 0;
784 u32 pin_reg;
785 unsigned long flags;
786 enum pin_config_param param;
787 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
788
789 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
790 for (i = 0; i < num_configs; i++) {
791 param = pinconf_to_config_param(configs[i]);
792 arg = pinconf_to_config_argument(configs[i]);
793 pin_reg = readl(gpio_dev->base + pin*4);
794
795 switch (param) {
796 case PIN_CONFIG_INPUT_DEBOUNCE:
797 ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
798 goto out_unlock;
799
800 case PIN_CONFIG_BIAS_PULL_DOWN:
801 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
802 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
803 break;
804
805 case PIN_CONFIG_BIAS_PULL_UP:
806 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
807 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF;
808 break;
809
810 case PIN_CONFIG_DRIVE_STRENGTH:
811 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
812 << DRV_STRENGTH_SEL_OFF);
813 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
814 << DRV_STRENGTH_SEL_OFF;
815 break;
816
817 default:
818 dev_dbg(&gpio_dev->pdev->dev,
819 "Invalid config param %04x\n", param);
820 ret = -ENOTSUPP;
821 }
822
823 writel(pin_reg, gpio_dev->base + pin*4);
824 }
825 out_unlock:
826 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
827
828 return ret;
829 }
830
amd_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)831 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
832 unsigned int group,
833 unsigned long *config)
834 {
835 const unsigned *pins;
836 unsigned npins;
837 int ret;
838
839 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
840 if (ret)
841 return ret;
842
843 if (amd_pinconf_get(pctldev, pins[0], config))
844 return -ENOTSUPP;
845
846 return 0;
847 }
848
amd_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)849 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
850 unsigned group, unsigned long *configs,
851 unsigned num_configs)
852 {
853 const unsigned *pins;
854 unsigned npins;
855 int i, ret;
856
857 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
858 if (ret)
859 return ret;
860 for (i = 0; i < npins; i++) {
861 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
862 return -ENOTSUPP;
863 }
864 return 0;
865 }
866
amd_gpio_set_config(struct gpio_chip * gc,unsigned int pin,unsigned long config)867 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
868 unsigned long config)
869 {
870 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
871
872 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
873 }
874
875 static const struct pinconf_ops amd_pinconf_ops = {
876 .pin_config_get = amd_pinconf_get,
877 .pin_config_set = amd_pinconf_set,
878 .pin_config_group_get = amd_pinconf_group_get,
879 .pin_config_group_set = amd_pinconf_group_set,
880 };
881
amd_gpio_irq_init(struct amd_gpio * gpio_dev)882 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
883 {
884 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
885 unsigned long flags;
886 u32 pin_reg, mask;
887 int i;
888
889 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
890 BIT(WAKE_CNTRL_OFF_S4);
891
892 for (i = 0; i < desc->npins; i++) {
893 int pin = desc->pins[i].number;
894 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
895
896 if (!pd)
897 continue;
898
899 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
900
901 pin_reg = readl(gpio_dev->base + pin * 4);
902 pin_reg &= ~mask;
903 writel(pin_reg, gpio_dev->base + pin * 4);
904
905 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
906 }
907 }
908
909 #if defined(CONFIG_SUSPEND) && defined(CONFIG_ACPI)
amd_gpio_check_pending(void)910 static void amd_gpio_check_pending(void)
911 {
912 struct amd_gpio *gpio_dev = pinctrl_dev;
913 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
914 int i;
915
916 if (!pm_debug_messages_on)
917 return;
918
919 for (i = 0; i < desc->npins; i++) {
920 int pin = desc->pins[i].number;
921 u32 tmp;
922
923 tmp = readl(gpio_dev->base + pin * 4);
924 if (tmp & PIN_IRQ_PENDING)
925 pm_pr_dbg("%s: GPIO %d is active: 0x%x.\n", __func__, pin, tmp);
926 }
927 }
928
929 static struct acpi_s2idle_dev_ops pinctrl_amd_s2idle_dev_ops = {
930 .check = amd_gpio_check_pending,
931 };
932
amd_gpio_register_s2idle_ops(void)933 static void amd_gpio_register_s2idle_ops(void)
934 {
935 acpi_register_lps0_dev(&pinctrl_amd_s2idle_dev_ops);
936 }
937
amd_gpio_unregister_s2idle_ops(void)938 static void amd_gpio_unregister_s2idle_ops(void)
939 {
940 acpi_unregister_lps0_dev(&pinctrl_amd_s2idle_dev_ops);
941 }
942 #else
amd_gpio_register_s2idle_ops(void)943 static inline void amd_gpio_register_s2idle_ops(void) {}
amd_gpio_unregister_s2idle_ops(void)944 static inline void amd_gpio_unregister_s2idle_ops(void) {}
945 #endif
946
947 #ifdef CONFIG_PM_SLEEP
amd_gpio_should_save(struct amd_gpio * gpio_dev,unsigned int pin)948 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
949 {
950 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
951
952 if (!pd)
953 return false;
954
955 /*
956 * Only restore the pin if it is actually in use by the kernel (or
957 * by userspace).
958 */
959 if (pd->mux_owner || pd->gpio_owner ||
960 gpiochip_line_is_irq(&gpio_dev->gc, pin))
961 return true;
962
963 return false;
964 }
965
amd_gpio_suspend_hibernate_common(struct device * dev,bool is_suspend)966 static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend)
967 {
968 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
969 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
970 unsigned long flags;
971 int i;
972 u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE;
973
974 for (i = 0; i < desc->npins; i++) {
975 int pin = desc->pins[i].number;
976
977 if (!amd_gpio_should_save(gpio_dev, pin))
978 continue;
979
980 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
981 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
982
983 /* mask any interrupts not intended to be a wake source */
984 if (!(gpio_dev->saved_regs[i] & wake_mask)) {
985 writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF),
986 gpio_dev->base + pin * 4);
987 pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n",
988 pin, is_suspend ? "suspend" : "hibernate");
989 }
990
991 /*
992 * debounce enabled over suspend has shown issues with a GPIO
993 * being unable to wake the system, as we're only interested in
994 * the actual wakeup event, clear it.
995 */
996 if (gpio_dev->saved_regs[i] & (DB_CNTRl_MASK << DB_CNTRL_OFF)) {
997 amd_gpio_set_debounce(gpio_dev, pin, 0);
998 pm_pr_dbg("Clearing debounce for GPIO #%d during %s.\n",
999 pin, is_suspend ? "suspend" : "hibernate");
1000 }
1001
1002 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
1003 }
1004
1005 return 0;
1006 }
1007
amd_gpio_suspend(struct device * dev)1008 static int amd_gpio_suspend(struct device *dev)
1009 {
1010 #ifdef CONFIG_SUSPEND
1011 pinctrl_dev = dev_get_drvdata(dev);
1012 #endif
1013 return amd_gpio_suspend_hibernate_common(dev, true);
1014 }
1015
amd_gpio_hibernate(struct device * dev)1016 static int amd_gpio_hibernate(struct device *dev)
1017 {
1018 return amd_gpio_suspend_hibernate_common(dev, false);
1019 }
1020
amd_gpio_resume(struct device * dev)1021 static int amd_gpio_resume(struct device *dev)
1022 {
1023 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
1024 const struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
1025 unsigned long flags;
1026 int i;
1027
1028 for (i = 0; i < desc->npins; i++) {
1029 int pin = desc->pins[i].number;
1030
1031 if (!amd_gpio_should_save(gpio_dev, pin))
1032 continue;
1033
1034 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
1035 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
1036 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
1037 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
1038 }
1039
1040 return 0;
1041 }
1042
1043 static const struct dev_pm_ops amd_gpio_pm_ops = {
1044 .suspend_late = amd_gpio_suspend,
1045 .resume_early = amd_gpio_resume,
1046 .freeze_late = amd_gpio_hibernate,
1047 .thaw_early = amd_gpio_resume,
1048 .poweroff_late = amd_gpio_hibernate,
1049 .restore_early = amd_gpio_resume,
1050 };
1051 #endif
1052
amd_get_functions_count(struct pinctrl_dev * pctldev)1053 static int amd_get_functions_count(struct pinctrl_dev *pctldev)
1054 {
1055 return ARRAY_SIZE(pmx_functions);
1056 }
1057
amd_get_fname(struct pinctrl_dev * pctrldev,unsigned int selector)1058 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
1059 {
1060 return pmx_functions[selector].name;
1061 }
1062
amd_get_groups(struct pinctrl_dev * pctrldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)1063 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
1064 const char * const **groups,
1065 unsigned int * const num_groups)
1066 {
1067 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
1068
1069 if (!gpio_dev->iomux_base) {
1070 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
1071 return -EINVAL;
1072 }
1073
1074 *groups = pmx_functions[selector].groups;
1075 *num_groups = pmx_functions[selector].ngroups;
1076 return 0;
1077 }
1078
amd_set_mux(struct pinctrl_dev * pctrldev,unsigned int function,unsigned int group)1079 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
1080 {
1081 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
1082 struct device *dev = &gpio_dev->pdev->dev;
1083 struct pin_desc *pd;
1084 int ind, index;
1085
1086 if (!gpio_dev->iomux_base)
1087 return -EINVAL;
1088
1089 for (index = 0; index < NSELECTS; index++) {
1090 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index]))
1091 continue;
1092
1093 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
1094 FUNCTION_INVALID) {
1095 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1096 pmx_functions[function].index);
1097 return -EINVAL;
1098 }
1099
1100 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
1101
1102 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
1103 FUNCTION_MASK)) {
1104 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1105 pmx_functions[function].index);
1106 return -EINVAL;
1107 }
1108
1109 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
1110 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
1111 continue;
1112
1113 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
1114 pd->mux_owner = gpio_dev->groups[group].name;
1115 }
1116 break;
1117 }
1118
1119 return 0;
1120 }
1121
1122 static const struct pinmux_ops amd_pmxops = {
1123 .get_functions_count = amd_get_functions_count,
1124 .get_function_name = amd_get_fname,
1125 .get_function_groups = amd_get_groups,
1126 .set_mux = amd_set_mux,
1127 };
1128
1129 static struct pinctrl_desc amd_pinctrl_desc = {
1130 .pins = kerncz_pins,
1131 .npins = ARRAY_SIZE(kerncz_pins),
1132 .pctlops = &amd_pinctrl_ops,
1133 .pmxops = &amd_pmxops,
1134 .confops = &amd_pinconf_ops,
1135 .owner = THIS_MODULE,
1136 };
1137
amd_get_iomux_res(struct amd_gpio * gpio_dev)1138 static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
1139 {
1140 struct pinctrl_desc *desc = &amd_pinctrl_desc;
1141 struct device *dev = &gpio_dev->pdev->dev;
1142 int index;
1143
1144 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
1145 if (index < 0) {
1146 dev_dbg(dev, "iomux not supported\n");
1147 goto out_no_pinmux;
1148 }
1149
1150 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
1151 if (IS_ERR(gpio_dev->iomux_base)) {
1152 dev_dbg(dev, "iomux not supported %d io resource\n", index);
1153 goto out_no_pinmux;
1154 }
1155
1156 return;
1157
1158 out_no_pinmux:
1159 desc->pmxops = NULL;
1160 }
1161
amd_gpio_probe(struct platform_device * pdev)1162 static int amd_gpio_probe(struct platform_device *pdev)
1163 {
1164 int ret = 0;
1165 struct resource *res;
1166 struct amd_gpio *gpio_dev;
1167 struct gpio_irq_chip *girq;
1168
1169 gpio_dev = devm_kzalloc(&pdev->dev,
1170 sizeof(struct amd_gpio), GFP_KERNEL);
1171 if (!gpio_dev)
1172 return -ENOMEM;
1173
1174 raw_spin_lock_init(&gpio_dev->lock);
1175
1176 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1177 if (IS_ERR(gpio_dev->base)) {
1178 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
1179 return PTR_ERR(gpio_dev->base);
1180 }
1181
1182 gpio_dev->irq = platform_get_irq(pdev, 0);
1183 if (gpio_dev->irq < 0)
1184 return gpio_dev->irq;
1185
1186 #ifdef CONFIG_SUSPEND
1187 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
1188 sizeof(*gpio_dev->saved_regs),
1189 GFP_KERNEL);
1190 if (!gpio_dev->saved_regs)
1191 return -ENOMEM;
1192 #endif
1193
1194 gpio_dev->pdev = pdev;
1195 gpio_dev->gc.get_direction = amd_gpio_get_direction;
1196 gpio_dev->gc.direction_input = amd_gpio_direction_input;
1197 gpio_dev->gc.direction_output = amd_gpio_direction_output;
1198 gpio_dev->gc.get = amd_gpio_get_value;
1199 gpio_dev->gc.set = amd_gpio_set_value;
1200 gpio_dev->gc.set_config = amd_gpio_set_config;
1201 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
1202
1203 gpio_dev->gc.base = -1;
1204 gpio_dev->gc.label = pdev->name;
1205 gpio_dev->gc.owner = THIS_MODULE;
1206 gpio_dev->gc.parent = &pdev->dev;
1207 gpio_dev->gc.ngpio = resource_size(res) / 4;
1208
1209 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
1210 gpio_dev->groups = kerncz_groups;
1211 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
1212
1213 amd_pinctrl_desc.name = dev_name(&pdev->dev);
1214 amd_get_iomux_res(gpio_dev);
1215 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
1216 gpio_dev);
1217 if (IS_ERR(gpio_dev->pctrl)) {
1218 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1219 return PTR_ERR(gpio_dev->pctrl);
1220 }
1221
1222 /* Disable and mask interrupts */
1223 amd_gpio_irq_init(gpio_dev);
1224
1225 girq = &gpio_dev->gc.irq;
1226 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
1227 /* This will let us handle the parent IRQ in the driver */
1228 girq->parent_handler = NULL;
1229 girq->num_parents = 0;
1230 girq->parents = NULL;
1231 girq->default_type = IRQ_TYPE_NONE;
1232 girq->handler = handle_simple_irq;
1233
1234 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
1235 if (ret)
1236 return ret;
1237
1238 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
1239 0, 0, gpio_dev->gc.ngpio);
1240 if (ret) {
1241 dev_err(&pdev->dev, "Failed to add pin range\n");
1242 goto out2;
1243 }
1244
1245 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
1246 IRQF_SHARED | IRQF_COND_ONESHOT, KBUILD_MODNAME, gpio_dev);
1247 if (ret)
1248 goto out2;
1249
1250 platform_set_drvdata(pdev, gpio_dev);
1251 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
1252 amd_gpio_register_s2idle_ops();
1253
1254 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1255 return ret;
1256
1257 out2:
1258 gpiochip_remove(&gpio_dev->gc);
1259
1260 return ret;
1261 }
1262
amd_gpio_remove(struct platform_device * pdev)1263 static void amd_gpio_remove(struct platform_device *pdev)
1264 {
1265 struct amd_gpio *gpio_dev;
1266
1267 gpio_dev = platform_get_drvdata(pdev);
1268
1269 gpiochip_remove(&gpio_dev->gc);
1270 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
1271 amd_gpio_unregister_s2idle_ops();
1272 }
1273
1274 #ifdef CONFIG_ACPI
1275 static const struct acpi_device_id amd_gpio_acpi_match[] = {
1276 { "AMD0030", 0 },
1277 { "AMDI0030", 0},
1278 { "AMDI0031", 0},
1279 { },
1280 };
1281 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1282 #endif
1283
1284 static struct platform_driver amd_gpio_driver = {
1285 .driver = {
1286 .name = "amd_gpio",
1287 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
1288 #ifdef CONFIG_PM_SLEEP
1289 .pm = &amd_gpio_pm_ops,
1290 #endif
1291 },
1292 .probe = amd_gpio_probe,
1293 .remove = amd_gpio_remove,
1294 };
1295
1296 module_platform_driver(amd_gpio_driver);
1297
1298 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
1299 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
1300