1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments TSC2046 SPI ADC driver
4 *
5 * Copyright (c) 2021 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/cleanup.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/spi/spi.h>
14 #include <linux/units.h>
15
16 #include <linux/unaligned.h>
17
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/iio/trigger.h>
22
23 /*
24 * The PENIRQ of TSC2046 controller is implemented as level shifter attached to
25 * the X+ line. If voltage of the X+ line reaches a specific level the IRQ will
26 * be activated or deactivated.
27 * To make this kind of IRQ reusable as trigger following additions were
28 * implemented:
29 * - rate limiting:
30 * For typical touchscreen use case, we need to trigger about each 10ms.
31 * - hrtimer:
32 * Continue triggering at least once after the IRQ was deactivated. Then
33 * deactivate this trigger to stop sampling in order to reduce power
34 * consumption.
35 */
36
37 #define TI_TSC2046_NAME "tsc2046"
38
39 /* This driver doesn't aim at the peak continuous sample rate */
40 #define TI_TSC2046_MAX_SAMPLE_RATE 125000
41 #define TI_TSC2046_SAMPLE_BITS \
42 BITS_PER_TYPE(struct tsc2046_adc_atom)
43 #define TI_TSC2046_MAX_CLK_FREQ \
44 (TI_TSC2046_MAX_SAMPLE_RATE * TI_TSC2046_SAMPLE_BITS)
45
46 #define TI_TSC2046_SAMPLE_INTERVAL_US 10000
47
48 #define TI_TSC2046_START BIT(7)
49 #define TI_TSC2046_ADDR GENMASK(6, 4)
50 #define TI_TSC2046_ADDR_TEMP1 7
51 #define TI_TSC2046_ADDR_AUX 6
52 #define TI_TSC2046_ADDR_X 5
53 #define TI_TSC2046_ADDR_Z2 4
54 #define TI_TSC2046_ADDR_Z1 3
55 #define TI_TSC2046_ADDR_VBAT 2
56 #define TI_TSC2046_ADDR_Y 1
57 #define TI_TSC2046_ADDR_TEMP0 0
58
59 /*
60 * The mode bit sets the resolution of the ADC. With this bit low, the next
61 * conversion has 12-bit resolution, whereas with this bit high, the next
62 * conversion has 8-bit resolution. This driver is optimized for 12-bit mode.
63 * So, for this driver, this bit should stay zero.
64 */
65 #define TI_TSC2046_8BIT_MODE BIT(3)
66
67 /*
68 * SER/DFR - The SER/DFR bit controls the reference mode, either single-ended
69 * (high) or differential (low).
70 */
71 #define TI_TSC2046_SER BIT(2)
72
73 /*
74 * If VREF_ON and ADC_ON are both zero, then the chip operates in
75 * auto-wake/suspend mode. In most case this bits should stay zero.
76 */
77 #define TI_TSC2046_PD1_VREF_ON BIT(1)
78 #define TI_TSC2046_PD0_ADC_ON BIT(0)
79
80 /*
81 * All supported devices can do 8 or 12bit resolution. This driver
82 * supports only 12bit mode, here we have a 16bit data transfer, where
83 * the MSB and the 3 LSB are 0.
84 */
85 #define TI_TSC2046_DATA_12BIT GENMASK(14, 3)
86
87 #define TI_TSC2046_MAX_CHAN 8
88 #define TI_TSC2046_MIN_POLL_CNT 3
89 #define TI_TSC2046_EXT_POLL_CNT 3
90 #define TI_TSC2046_POLL_CNT \
91 (TI_TSC2046_MIN_POLL_CNT + TI_TSC2046_EXT_POLL_CNT)
92 #define TI_TSC2046_INT_VREF 2500
93
94 /* Represents a HW sample */
95 struct tsc2046_adc_atom {
96 /*
97 * Command transmitted to the controller. This field is empty on the RX
98 * buffer.
99 */
100 u8 cmd;
101 /*
102 * Data received from the controller. This field is empty for the TX
103 * buffer
104 */
105 __be16 data;
106 } __packed;
107
108 /* Layout of atomic buffers within big buffer */
109 struct tsc2046_adc_group_layout {
110 /* Group offset within the SPI RX buffer */
111 unsigned int offset;
112 /*
113 * Amount of tsc2046_adc_atom structs within the same command gathered
114 * within same group.
115 */
116 unsigned int count;
117 /*
118 * Settling samples (tsc2046_adc_atom structs) which should be skipped
119 * before good samples will start.
120 */
121 unsigned int skip;
122 };
123
124 struct tsc2046_adc_dcfg {
125 const struct iio_chan_spec *channels;
126 unsigned int num_channels;
127 };
128
129 struct tsc2046_adc_ch_cfg {
130 unsigned int settling_time_us;
131 unsigned int oversampling_ratio;
132 };
133
134 enum tsc2046_state {
135 TSC2046_STATE_SHUTDOWN,
136 TSC2046_STATE_STANDBY,
137 TSC2046_STATE_POLL,
138 TSC2046_STATE_POLL_IRQ_DISABLE,
139 TSC2046_STATE_ENABLE_IRQ,
140 };
141
142 struct tsc2046_adc_priv {
143 struct spi_device *spi;
144 const struct tsc2046_adc_dcfg *dcfg;
145 bool internal_vref;
146
147 struct iio_trigger *trig;
148 struct hrtimer trig_timer;
149 enum tsc2046_state state;
150 int poll_cnt;
151 spinlock_t state_lock;
152
153 struct spi_transfer xfer;
154 struct spi_message msg;
155
156 struct {
157 /* Scan data for each channel */
158 u16 data[TI_TSC2046_MAX_CHAN];
159 /* Timestamp */
160 aligned_s64 ts;
161 } scan_buf;
162
163 /*
164 * Lock to protect the layout and the SPI transfer buffer.
165 * tsc2046_adc_group_layout can be changed within update_scan_mode(),
166 * in this case the l[] and tx/rx buffer will be out of sync to each
167 * other.
168 */
169 struct mutex slock;
170 struct tsc2046_adc_group_layout l[TI_TSC2046_MAX_CHAN];
171 struct tsc2046_adc_atom *rx;
172 struct tsc2046_adc_atom *tx;
173
174 unsigned int count;
175 unsigned int groups;
176 u32 effective_speed_hz;
177 u32 scan_interval_us;
178 u32 time_per_scan_us;
179 u32 time_per_bit_ns;
180 unsigned int vref_mv;
181
182 struct tsc2046_adc_ch_cfg ch_cfg[TI_TSC2046_MAX_CHAN];
183 };
184
185 #define TI_TSC2046_V_CHAN(index, bits, name) \
186 { \
187 .type = IIO_VOLTAGE, \
188 .indexed = 1, \
189 .channel = index, \
190 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
191 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
192 .datasheet_name = "#name", \
193 .scan_index = index, \
194 .scan_type = { \
195 .sign = 'u', \
196 .realbits = bits, \
197 .storagebits = 16, \
198 .endianness = IIO_CPU, \
199 }, \
200 }
201
202 #define DECLARE_TI_TSC2046_8_CHANNELS(name, bits) \
203 const struct iio_chan_spec name ## _channels[] = { \
204 TI_TSC2046_V_CHAN(0, bits, TEMP0), \
205 TI_TSC2046_V_CHAN(1, bits, Y), \
206 TI_TSC2046_V_CHAN(2, bits, VBAT), \
207 TI_TSC2046_V_CHAN(3, bits, Z1), \
208 TI_TSC2046_V_CHAN(4, bits, Z2), \
209 TI_TSC2046_V_CHAN(5, bits, X), \
210 TI_TSC2046_V_CHAN(6, bits, AUX), \
211 TI_TSC2046_V_CHAN(7, bits, TEMP1), \
212 IIO_CHAN_SOFT_TIMESTAMP(8), \
213 }
214
215 static DECLARE_TI_TSC2046_8_CHANNELS(tsc2046_adc, 12);
216
217 static const struct tsc2046_adc_dcfg tsc2046_adc_dcfg_tsc2046e = {
218 .channels = tsc2046_adc_channels,
219 .num_channels = ARRAY_SIZE(tsc2046_adc_channels),
220 };
221
222 /*
223 * Convert time to a number of samples which can be transferred within this
224 * time.
225 */
tsc2046_adc_time_to_count(struct tsc2046_adc_priv * priv,unsigned long time)226 static unsigned int tsc2046_adc_time_to_count(struct tsc2046_adc_priv *priv,
227 unsigned long time)
228 {
229 unsigned int bit_count, sample_count;
230
231 bit_count = DIV_ROUND_UP(time * NSEC_PER_USEC, priv->time_per_bit_ns);
232 sample_count = DIV_ROUND_UP(bit_count, TI_TSC2046_SAMPLE_BITS);
233
234 dev_dbg(&priv->spi->dev, "Effective speed %u, time per bit: %u, count bits: %u, count samples: %u\n",
235 priv->effective_speed_hz, priv->time_per_bit_ns,
236 bit_count, sample_count);
237
238 return sample_count;
239 }
240
tsc2046_adc_get_cmd(struct tsc2046_adc_priv * priv,int ch_idx,bool keep_power)241 static u8 tsc2046_adc_get_cmd(struct tsc2046_adc_priv *priv, int ch_idx,
242 bool keep_power)
243 {
244 u32 pd;
245
246 /*
247 * if PD bits are 0, controller will automatically disable ADC, VREF and
248 * enable IRQ.
249 */
250 if (keep_power)
251 pd = TI_TSC2046_PD0_ADC_ON;
252 else
253 pd = 0;
254
255 switch (ch_idx) {
256 case TI_TSC2046_ADDR_TEMP1:
257 case TI_TSC2046_ADDR_AUX:
258 case TI_TSC2046_ADDR_VBAT:
259 case TI_TSC2046_ADDR_TEMP0:
260 pd |= TI_TSC2046_SER;
261 if (priv->internal_vref)
262 pd |= TI_TSC2046_PD1_VREF_ON;
263 }
264
265 return TI_TSC2046_START | FIELD_PREP(TI_TSC2046_ADDR, ch_idx) | pd;
266 }
267
tsc2046_adc_get_value(struct tsc2046_adc_atom * buf)268 static u16 tsc2046_adc_get_value(struct tsc2046_adc_atom *buf)
269 {
270 return FIELD_GET(TI_TSC2046_DATA_12BIT, get_unaligned_be16(&buf->data));
271 }
272
tsc2046_adc_read_one(struct tsc2046_adc_priv * priv,int ch_idx,u32 * effective_speed_hz)273 static int tsc2046_adc_read_one(struct tsc2046_adc_priv *priv, int ch_idx,
274 u32 *effective_speed_hz)
275 {
276 struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx];
277 unsigned int val, val_normalized = 0;
278 int ret, i, count_skip = 0, max_count;
279 struct spi_transfer xfer = { };
280 struct spi_message msg;
281 u8 cmd;
282
283 if (!effective_speed_hz) {
284 count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us);
285 max_count = count_skip + ch->oversampling_ratio;
286 } else {
287 max_count = 1;
288 }
289
290 if (sizeof(struct tsc2046_adc_atom) * max_count > PAGE_SIZE)
291 return -ENOSPC;
292
293 struct tsc2046_adc_atom *tx_buf __free(kfree) = kcalloc(max_count,
294 sizeof(*tx_buf),
295 GFP_KERNEL);
296 if (!tx_buf)
297 return -ENOMEM;
298
299 struct tsc2046_adc_atom *rx_buf __free(kfree) = kcalloc(max_count,
300 sizeof(*rx_buf),
301 GFP_KERNEL);
302 if (!rx_buf)
303 return -ENOMEM;
304
305 /*
306 * Do not enable automatic power down on working samples. Otherwise the
307 * plates will never be completely charged.
308 */
309 cmd = tsc2046_adc_get_cmd(priv, ch_idx, true);
310
311 for (i = 0; i < max_count - 1; i++)
312 tx_buf[i].cmd = cmd;
313
314 /* automatically power down on last sample */
315 tx_buf[i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
316
317 xfer.tx_buf = tx_buf;
318 xfer.rx_buf = rx_buf;
319 xfer.len = sizeof(*tx_buf) * max_count;
320 spi_message_init_with_transfers(&msg, &xfer, 1);
321
322 /*
323 * We aren't using spi_write_then_read() because we need to be able
324 * to get hold of the effective_speed_hz from the xfer
325 */
326 ret = spi_sync(priv->spi, &msg);
327 if (ret) {
328 dev_err_ratelimited(&priv->spi->dev, "SPI transfer failed %pe\n",
329 ERR_PTR(ret));
330 return ret;
331 }
332
333 if (effective_speed_hz)
334 *effective_speed_hz = xfer.effective_speed_hz;
335
336 for (i = 0; i < max_count - count_skip; i++) {
337 val = tsc2046_adc_get_value(&rx_buf[count_skip + i]);
338 val_normalized += val;
339 }
340
341 return DIV_ROUND_UP(val_normalized, max_count - count_skip);
342 }
343
tsc2046_adc_group_set_layout(struct tsc2046_adc_priv * priv,unsigned int group,unsigned int ch_idx)344 static size_t tsc2046_adc_group_set_layout(struct tsc2046_adc_priv *priv,
345 unsigned int group,
346 unsigned int ch_idx)
347 {
348 struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx];
349 struct tsc2046_adc_group_layout *cur;
350 unsigned int max_count, count_skip;
351 unsigned int offset = 0;
352
353 if (group)
354 offset = priv->l[group - 1].offset + priv->l[group - 1].count;
355
356 count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us);
357 max_count = count_skip + ch->oversampling_ratio;
358
359 cur = &priv->l[group];
360 cur->offset = offset;
361 cur->count = max_count;
362 cur->skip = count_skip;
363
364 return sizeof(*priv->tx) * max_count;
365 }
366
tsc2046_adc_group_set_cmd(struct tsc2046_adc_priv * priv,unsigned int group,int ch_idx)367 static void tsc2046_adc_group_set_cmd(struct tsc2046_adc_priv *priv,
368 unsigned int group, int ch_idx)
369 {
370 struct tsc2046_adc_group_layout *l = &priv->l[group];
371 unsigned int i;
372 u8 cmd;
373
374 /*
375 * Do not enable automatic power down on working samples. Otherwise the
376 * plates will never be completely charged.
377 */
378 cmd = tsc2046_adc_get_cmd(priv, ch_idx, true);
379
380 for (i = 0; i < l->count - 1; i++)
381 priv->tx[l->offset + i].cmd = cmd;
382
383 /* automatically power down on last sample */
384 priv->tx[l->offset + i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
385 }
386
tsc2046_adc_get_val(struct tsc2046_adc_priv * priv,int group)387 static u16 tsc2046_adc_get_val(struct tsc2046_adc_priv *priv, int group)
388 {
389 struct tsc2046_adc_group_layout *l;
390 unsigned int val, val_normalized = 0;
391 int valid_count, i;
392
393 l = &priv->l[group];
394 valid_count = l->count - l->skip;
395
396 for (i = 0; i < valid_count; i++) {
397 val = tsc2046_adc_get_value(&priv->rx[l->offset + l->skip + i]);
398 val_normalized += val;
399 }
400
401 return DIV_ROUND_UP(val_normalized, valid_count);
402 }
403
tsc2046_adc_scan(struct iio_dev * indio_dev)404 static int tsc2046_adc_scan(struct iio_dev *indio_dev)
405 {
406 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
407 struct device *dev = &priv->spi->dev;
408 int group;
409 int ret;
410
411 ret = spi_sync(priv->spi, &priv->msg);
412 if (ret < 0) {
413 dev_err_ratelimited(dev, "SPI transfer failed: %pe\n", ERR_PTR(ret));
414 return ret;
415 }
416
417 for (group = 0; group < priv->groups; group++)
418 priv->scan_buf.data[group] = tsc2046_adc_get_val(priv, group);
419
420 ret = iio_push_to_buffers_with_ts(indio_dev, &priv->scan_buf,
421 sizeof(priv->scan_buf),
422 iio_get_time_ns(indio_dev));
423 /* If the consumer is kfifo, we may get a EBUSY here - ignore it. */
424 if (ret < 0 && ret != -EBUSY) {
425 dev_err_ratelimited(dev, "Failed to push scan buffer %pe\n",
426 ERR_PTR(ret));
427
428 return ret;
429 }
430
431 return 0;
432 }
433
tsc2046_adc_trigger_handler(int irq,void * p)434 static irqreturn_t tsc2046_adc_trigger_handler(int irq, void *p)
435 {
436 struct iio_poll_func *pf = p;
437 struct iio_dev *indio_dev = pf->indio_dev;
438 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
439
440 mutex_lock(&priv->slock);
441 tsc2046_adc_scan(indio_dev);
442 mutex_unlock(&priv->slock);
443
444 iio_trigger_notify_done(indio_dev->trig);
445
446 return IRQ_HANDLED;
447 }
448
tsc2046_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)449 static int tsc2046_adc_read_raw(struct iio_dev *indio_dev,
450 struct iio_chan_spec const *chan,
451 int *val, int *val2, long m)
452 {
453 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
454 int ret;
455
456 switch (m) {
457 case IIO_CHAN_INFO_RAW:
458 ret = tsc2046_adc_read_one(priv, chan->channel, NULL);
459 if (ret < 0)
460 return ret;
461
462 *val = ret;
463
464 return IIO_VAL_INT;
465 case IIO_CHAN_INFO_SCALE:
466 /*
467 * Note: the TSC2046 has internal voltage divider on the VBAT
468 * line. This divider can be influenced by external divider.
469 * So, it is better to use external voltage-divider driver
470 * instead, which is calculating complete chain.
471 */
472 *val = priv->vref_mv;
473 *val2 = chan->scan_type.realbits;
474 return IIO_VAL_FRACTIONAL_LOG2;
475 }
476
477 return -EINVAL;
478 }
479
tsc2046_adc_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)480 static int tsc2046_adc_update_scan_mode(struct iio_dev *indio_dev,
481 const unsigned long *active_scan_mask)
482 {
483 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
484 unsigned int ch_idx, group = 0;
485 size_t size;
486
487 mutex_lock(&priv->slock);
488
489 size = 0;
490 for_each_set_bit(ch_idx, active_scan_mask, ARRAY_SIZE(priv->l)) {
491 size += tsc2046_adc_group_set_layout(priv, group, ch_idx);
492 tsc2046_adc_group_set_cmd(priv, group, ch_idx);
493 group++;
494 }
495
496 priv->groups = group;
497 priv->xfer.len = size;
498 priv->time_per_scan_us = size * 8 * priv->time_per_bit_ns / NSEC_PER_USEC;
499
500 if (priv->scan_interval_us < priv->time_per_scan_us)
501 dev_warn(&priv->spi->dev, "The scan interval (%d) is less then calculated scan time (%d)\n",
502 priv->scan_interval_us, priv->time_per_scan_us);
503
504 mutex_unlock(&priv->slock);
505
506 return 0;
507 }
508
509 static const struct iio_info tsc2046_adc_info = {
510 .read_raw = tsc2046_adc_read_raw,
511 .update_scan_mode = tsc2046_adc_update_scan_mode,
512 };
513
tsc2046_adc_timer(struct hrtimer * hrtimer)514 static enum hrtimer_restart tsc2046_adc_timer(struct hrtimer *hrtimer)
515 {
516 struct tsc2046_adc_priv *priv = container_of(hrtimer,
517 struct tsc2046_adc_priv,
518 trig_timer);
519 unsigned long flags;
520
521 /*
522 * This state machine should address following challenges :
523 * - the interrupt source is based on level shifter attached to the X
524 * channel of ADC. It will change the state every time we switch
525 * between channels. So, we need to disable IRQ if we do
526 * iio_trigger_poll().
527 * - we should do iio_trigger_poll() at some reduced sample rate
528 * - we should still trigger for some amount of time after last
529 * interrupt with enabled IRQ was processed.
530 */
531
532 spin_lock_irqsave(&priv->state_lock, flags);
533 switch (priv->state) {
534 case TSC2046_STATE_ENABLE_IRQ:
535 if (priv->poll_cnt < TI_TSC2046_POLL_CNT) {
536 priv->poll_cnt++;
537 hrtimer_start(&priv->trig_timer,
538 us_to_ktime(priv->scan_interval_us),
539 HRTIMER_MODE_REL_SOFT);
540
541 if (priv->poll_cnt >= TI_TSC2046_MIN_POLL_CNT) {
542 priv->state = TSC2046_STATE_POLL_IRQ_DISABLE;
543 enable_irq(priv->spi->irq);
544 } else {
545 priv->state = TSC2046_STATE_POLL;
546 }
547 } else {
548 priv->state = TSC2046_STATE_STANDBY;
549 enable_irq(priv->spi->irq);
550 }
551 break;
552 case TSC2046_STATE_POLL_IRQ_DISABLE:
553 disable_irq_nosync(priv->spi->irq);
554 fallthrough;
555 case TSC2046_STATE_POLL:
556 priv->state = TSC2046_STATE_ENABLE_IRQ;
557 /* iio_trigger_poll() starts hrtimer */
558 iio_trigger_poll(priv->trig);
559 break;
560 case TSC2046_STATE_SHUTDOWN:
561 break;
562 case TSC2046_STATE_STANDBY:
563 fallthrough;
564 default:
565 dev_warn(&priv->spi->dev, "Got unexpected state: %i\n",
566 priv->state);
567 break;
568 }
569 spin_unlock_irqrestore(&priv->state_lock, flags);
570
571 return HRTIMER_NORESTART;
572 }
573
tsc2046_adc_irq(int irq,void * dev_id)574 static irqreturn_t tsc2046_adc_irq(int irq, void *dev_id)
575 {
576 struct iio_dev *indio_dev = dev_id;
577 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
578 unsigned long flags;
579
580 hrtimer_try_to_cancel(&priv->trig_timer);
581
582 spin_lock_irqsave(&priv->state_lock, flags);
583 if (priv->state != TSC2046_STATE_SHUTDOWN) {
584 priv->state = TSC2046_STATE_ENABLE_IRQ;
585 priv->poll_cnt = 0;
586
587 /* iio_trigger_poll() starts hrtimer */
588 disable_irq_nosync(priv->spi->irq);
589 iio_trigger_poll(priv->trig);
590 }
591 spin_unlock_irqrestore(&priv->state_lock, flags);
592
593 return IRQ_HANDLED;
594 }
595
tsc2046_adc_reenable_trigger(struct iio_trigger * trig)596 static void tsc2046_adc_reenable_trigger(struct iio_trigger *trig)
597 {
598 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
599 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
600 ktime_t tim;
601
602 /*
603 * We can sample it as fast as we can, but usually we do not need so
604 * many samples. Reduce the sample rate for default (touchscreen) use
605 * case.
606 */
607 tim = us_to_ktime(priv->scan_interval_us - priv->time_per_scan_us);
608 hrtimer_start(&priv->trig_timer, tim, HRTIMER_MODE_REL_SOFT);
609 }
610
tsc2046_adc_set_trigger_state(struct iio_trigger * trig,bool enable)611 static int tsc2046_adc_set_trigger_state(struct iio_trigger *trig, bool enable)
612 {
613 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
614 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
615 unsigned long flags;
616
617 if (enable) {
618 spin_lock_irqsave(&priv->state_lock, flags);
619 if (priv->state == TSC2046_STATE_SHUTDOWN) {
620 priv->state = TSC2046_STATE_STANDBY;
621 enable_irq(priv->spi->irq);
622 }
623 spin_unlock_irqrestore(&priv->state_lock, flags);
624 } else {
625 spin_lock_irqsave(&priv->state_lock, flags);
626
627 if (priv->state == TSC2046_STATE_STANDBY ||
628 priv->state == TSC2046_STATE_POLL_IRQ_DISABLE)
629 disable_irq_nosync(priv->spi->irq);
630
631 priv->state = TSC2046_STATE_SHUTDOWN;
632 spin_unlock_irqrestore(&priv->state_lock, flags);
633
634 hrtimer_cancel(&priv->trig_timer);
635 }
636
637 return 0;
638 }
639
640 static const struct iio_trigger_ops tsc2046_adc_trigger_ops = {
641 .set_trigger_state = tsc2046_adc_set_trigger_state,
642 .reenable = tsc2046_adc_reenable_trigger,
643 };
644
tsc2046_adc_setup_spi_msg(struct tsc2046_adc_priv * priv)645 static int tsc2046_adc_setup_spi_msg(struct tsc2046_adc_priv *priv)
646 {
647 unsigned int ch_idx;
648 size_t size;
649 int ret;
650
651 /*
652 * Make dummy read to set initial power state and get real SPI clock
653 * freq. It seems to be not important which channel is used for this
654 * case.
655 */
656 ret = tsc2046_adc_read_one(priv, TI_TSC2046_ADDR_TEMP0,
657 &priv->effective_speed_hz);
658 if (ret < 0)
659 return ret;
660
661 /*
662 * In case SPI controller do not report effective_speed_hz, use
663 * configure value and hope it will match.
664 */
665 if (!priv->effective_speed_hz)
666 priv->effective_speed_hz = priv->spi->max_speed_hz;
667
668
669 priv->scan_interval_us = TI_TSC2046_SAMPLE_INTERVAL_US;
670 priv->time_per_bit_ns = DIV_ROUND_UP(NSEC_PER_SEC,
671 priv->effective_speed_hz);
672
673 /*
674 * Calculate and allocate maximal size buffer if all channels are
675 * enabled.
676 */
677 size = 0;
678 for (ch_idx = 0; ch_idx < ARRAY_SIZE(priv->l); ch_idx++)
679 size += tsc2046_adc_group_set_layout(priv, ch_idx, ch_idx);
680
681 if (size > PAGE_SIZE) {
682 dev_err(&priv->spi->dev,
683 "Calculated scan buffer is too big. Try to reduce spi-max-frequency, settling-time-us or oversampling-ratio\n");
684 return -ENOSPC;
685 }
686
687 priv->tx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL);
688 if (!priv->tx)
689 return -ENOMEM;
690
691 priv->rx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL);
692 if (!priv->rx)
693 return -ENOMEM;
694
695 priv->xfer.tx_buf = priv->tx;
696 priv->xfer.rx_buf = priv->rx;
697 priv->xfer.len = size;
698 spi_message_init_with_transfers(&priv->msg, &priv->xfer, 1);
699
700 return 0;
701 }
702
tsc2046_adc_parse_fwnode(struct tsc2046_adc_priv * priv)703 static void tsc2046_adc_parse_fwnode(struct tsc2046_adc_priv *priv)
704 {
705 struct fwnode_handle *child;
706 struct device *dev = &priv->spi->dev;
707 unsigned int i;
708
709 for (i = 0; i < ARRAY_SIZE(priv->ch_cfg); i++) {
710 priv->ch_cfg[i].settling_time_us = 1;
711 priv->ch_cfg[i].oversampling_ratio = 1;
712 }
713
714 device_for_each_child_node(dev, child) {
715 u32 stl, overs, reg;
716 int ret;
717
718 ret = fwnode_property_read_u32(child, "reg", ®);
719 if (ret) {
720 dev_err(dev, "invalid reg on %pfw, err: %pe\n", child,
721 ERR_PTR(ret));
722 continue;
723 }
724
725 if (reg >= ARRAY_SIZE(priv->ch_cfg)) {
726 dev_err(dev, "%pfw: Unsupported reg value: %i, max supported is: %zu.\n",
727 child, reg, ARRAY_SIZE(priv->ch_cfg));
728 continue;
729 }
730
731 ret = fwnode_property_read_u32(child, "settling-time-us", &stl);
732 if (!ret)
733 priv->ch_cfg[reg].settling_time_us = stl;
734
735 ret = fwnode_property_read_u32(child, "oversampling-ratio",
736 &overs);
737 if (!ret)
738 priv->ch_cfg[reg].oversampling_ratio = overs;
739 }
740 }
741
tsc2046_adc_probe(struct spi_device * spi)742 static int tsc2046_adc_probe(struct spi_device *spi)
743 {
744 const struct tsc2046_adc_dcfg *dcfg;
745 struct device *dev = &spi->dev;
746 struct tsc2046_adc_priv *priv;
747 struct iio_dev *indio_dev;
748 struct iio_trigger *trig;
749 int ret;
750
751 if (spi->max_speed_hz > TI_TSC2046_MAX_CLK_FREQ) {
752 dev_err(dev, "SPI max_speed_hz is too high: %d Hz. Max supported freq is %zu Hz\n",
753 spi->max_speed_hz, TI_TSC2046_MAX_CLK_FREQ);
754 return -EINVAL;
755 }
756
757 dcfg = spi_get_device_match_data(spi);
758 if (!dcfg)
759 return -EINVAL;
760
761 spi->mode &= ~SPI_MODE_X_MASK;
762 spi->mode |= SPI_MODE_0;
763 ret = spi_setup(spi);
764 if (ret < 0)
765 return dev_err_probe(dev, ret, "Error in SPI setup\n");
766
767 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
768 if (!indio_dev)
769 return -ENOMEM;
770
771 priv = iio_priv(indio_dev);
772 priv->dcfg = dcfg;
773
774 priv->spi = spi;
775
776 indio_dev->name = TI_TSC2046_NAME;
777 indio_dev->modes = INDIO_DIRECT_MODE;
778 indio_dev->channels = dcfg->channels;
779 indio_dev->num_channels = dcfg->num_channels;
780 indio_dev->info = &tsc2046_adc_info;
781
782 ret = devm_regulator_get_enable_read_voltage(dev, "vref");
783 if (ret < 0 && ret != -ENODEV)
784 return ret;
785
786 priv->internal_vref = ret == -ENODEV;
787 priv->vref_mv = priv->internal_vref ? TI_TSC2046_INT_VREF : ret / MILLI;
788
789 tsc2046_adc_parse_fwnode(priv);
790
791 ret = tsc2046_adc_setup_spi_msg(priv);
792 if (ret)
793 return ret;
794
795 mutex_init(&priv->slock);
796
797 ret = devm_request_irq(dev, spi->irq, &tsc2046_adc_irq,
798 IRQF_NO_AUTOEN, indio_dev->name, indio_dev);
799 if (ret)
800 return ret;
801
802 trig = devm_iio_trigger_alloc(dev, "touchscreen-%s", indio_dev->name);
803 if (!trig)
804 return -ENOMEM;
805
806 priv->trig = trig;
807 iio_trigger_set_drvdata(trig, indio_dev);
808 trig->ops = &tsc2046_adc_trigger_ops;
809
810 spin_lock_init(&priv->state_lock);
811 priv->state = TSC2046_STATE_SHUTDOWN;
812 hrtimer_setup(&priv->trig_timer, tsc2046_adc_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_SOFT);
813
814 ret = devm_iio_trigger_register(dev, trig);
815 if (ret) {
816 dev_err(dev, "failed to register trigger\n");
817 return ret;
818 }
819
820 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
821 &tsc2046_adc_trigger_handler, NULL);
822 if (ret) {
823 dev_err(dev, "Failed to setup triggered buffer\n");
824 return ret;
825 }
826
827 /* set default trigger */
828 indio_dev->trig = iio_trigger_get(priv->trig);
829
830 return devm_iio_device_register(dev, indio_dev);
831 }
832
833 static const struct of_device_id ads7950_of_table[] = {
834 { .compatible = "ti,tsc2046e-adc", .data = &tsc2046_adc_dcfg_tsc2046e },
835 { }
836 };
837 MODULE_DEVICE_TABLE(of, ads7950_of_table);
838
839 static const struct spi_device_id tsc2046_adc_spi_ids[] = {
840 { "tsc2046e-adc", (unsigned long)&tsc2046_adc_dcfg_tsc2046e },
841 { }
842 };
843 MODULE_DEVICE_TABLE(spi, tsc2046_adc_spi_ids);
844
845 static struct spi_driver tsc2046_adc_driver = {
846 .driver = {
847 .name = "tsc2046",
848 .of_match_table = ads7950_of_table,
849 },
850 .id_table = tsc2046_adc_spi_ids,
851 .probe = tsc2046_adc_probe,
852 };
853 module_spi_driver(tsc2046_adc_driver);
854
855 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
856 MODULE_DESCRIPTION("TI TSC2046 ADC");
857 MODULE_LICENSE("GPL v2");
858