Searched hist:edadad80d65bf9c7aa9f2605dbd2eef94ccd47c0 (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/net/ethernet/chelsio/cxgb4/ |
| H A D | t4_values.h | edadad80d65bf9c7aa9f2605dbd2eef94ccd47c0 Tue Mar 01 11:49:33 UTC 2016 Hariprasad Shenai <hariprasad@chelsio.com> cxgb4/cxgb4vf: For T6 adapter, set FBMIN to 64 bytes
T4 and T5 hardware will not coalesce Free List PCI-E Fetch Requests if
the Host Driver provides more Free List Pointers than the Fetch Burst
Minimum value. So if we set FBMIN to 64 bytes and the Host Driver
supplies 128 bytes of Free List Pointer data, the hardware will issue two
64-byte PCI-E Fetch Requests rather than a single coallesced 128-byte
Fetch Request. T6 fixes this. So, for T4/T5 we set the FBMIN value to 128
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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| H A D | sge.c | edadad80d65bf9c7aa9f2605dbd2eef94ccd47c0 Tue Mar 01 11:49:33 UTC 2016 Hariprasad Shenai <hariprasad@chelsio.com> cxgb4/cxgb4vf: For T6 adapter, set FBMIN to 64 bytes
T4 and T5 hardware will not coalesce Free List PCI-E Fetch Requests if
the Host Driver provides more Free List Pointers than the Fetch Burst
Minimum value. So if we set FBMIN to 64 bytes and the Host Driver
supplies 128 bytes of Free List Pointer data, the hardware will issue two
64-byte PCI-E Fetch Requests rather than a single coallesced 128-byte
Fetch Request. T6 fixes this. So, for T4/T5 we set the FBMIN value to 128
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|
| /linux/drivers/net/ethernet/chelsio/cxgb4vf/ |
| H A D | sge.c | edadad80d65bf9c7aa9f2605dbd2eef94ccd47c0 Tue Mar 01 11:49:33 UTC 2016 Hariprasad Shenai <hariprasad@chelsio.com> cxgb4/cxgb4vf: For T6 adapter, set FBMIN to 64 bytes
T4 and T5 hardware will not coalesce Free List PCI-E Fetch Requests if
the Host Driver provides more Free List Pointers than the Fetch Burst
Minimum value. So if we set FBMIN to 64 bytes and the Host Driver
supplies 128 bytes of Free List Pointer data, the hardware will issue two
64-byte PCI-E Fetch Requests rather than a single coallesced 128-byte
Fetch Request. T6 fixes this. So, for T4/T5 we set the FBMIN value to 128
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
|