Searched hist:"6 a902b118e7f30dbf0e6248f7b0f97e12c0939c3" (Results 1 – 1 of 1) sorted by relevance
| /linux/drivers/clocksource/ |
| H A D | timer-riscv.c | 6a902b118e7f30dbf0e6248f7b0f97e12c0939c3 Thu Nov 16 10:53:12 UTC 2023 Joshua Yeong <joshua.yeong@starfivetech.com> clocksource/timer-riscv: Add riscv_clock_shutdown callback
Add clocksource detach/shutdown callback to disable RISC-V timer interrupt when
switching out riscv timer as clock source
Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20231116105312.4800-1-joshua.yeong@starfivetech.com
6a902b118e7f30dbf0e6248f7b0f97e12c0939c3 Thu Nov 16 10:53:12 UTC 2023 Joshua Yeong <joshua.yeong@starfivetech.com> clocksource/timer-riscv: Add riscv_clock_shutdown callback
Add clocksource detach/shutdown callback to disable RISC-V timer interrupt when
switching out riscv timer as clock source
Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20231116105312.4800-1-joshua.yeong@starfivetech.com
6a902b118e7f30dbf0e6248f7b0f97e12c0939c3 Thu Nov 16 10:53:12 UTC 2023 Joshua Yeong <joshua.yeong@starfivetech.com> clocksource/timer-riscv: Add riscv_clock_shutdown callback
Add clocksource detach/shutdown callback to disable RISC-V timer interrupt when
switching out riscv timer as clock source
Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20231116105312.4800-1-joshua.yeong@starfivetech.com
6a902b118e7f30dbf0e6248f7b0f97e12c0939c3 Thu Nov 16 10:53:12 UTC 2023 Joshua Yeong <joshua.yeong@starfivetech.com> clocksource/timer-riscv: Add riscv_clock_shutdown callback
Add clocksource detach/shutdown callback to disable RISC-V timer interrupt when
switching out riscv timer as clock source
Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20231116105312.4800-1-joshua.yeong@starfivetech.com
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