Searched +full:xmem +full:- +full:adv +full:- +full:to +full:- +full:oe +full:- +full:recovery +full:- +full:cycles (Results 1 – 3 of 3) sorted by relevance
| /linux-6.15/Documentation/devicetree/bindings/memory-controllers/ |
| D | qcom,ebi2-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
14 qcom,xmem-recovery-cycles:
17 The time the memory continues to drive the data bus after OE
18 is de-asserted, in order to avoid contention on the data bus.
19 They are inserted when reading one CS and switching to another
21 actually 1, so a value of 0 will still yield 1 recovery cycle.
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| D | qcom,ebi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
11 external memory (such as NAND or other memory-mapped peripherals) whereas
14 As it says it connects devices to an external bus interface, meaning address
15 lines (up to 9 address lines so can only address 1KiB external memory space),
16 data lines (16 bits), OE (output enable), ADV (address valid, used on some
22 unused they can be left unconnected or remuxed to be used as GPIO or in some
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| /linux-6.15/drivers/bus/ |
| D | qcom-ebi2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
43 * Inserted when reading one CS and switching to another CS or read
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
50 * write to a page or burst memory
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
52 * read to a page or burst memory
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
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