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Searched +full:tegra210 +full:- +full:emc (Results 1 – 14 of 14) sorted by relevance

/linux-5.10/drivers/memory/tegra/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
13 obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
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Dtegra210-emc-table.c1 // SPDX-License-Identifier: GPL-2.0
8 #include "tegra210-emc.h"
15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local
19 timings = memremap(rmem->base, rmem->size, MEMREMAP_WB); in tegra210_emc_table_device_init()
21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init()
22 return -ENOMEM; in tegra210_emc_table_device_init()
35 if (emc->derated) { in tegra210_emc_table_device_init()
36 dev_warn(dev, "excess EMC table '%s'\n", rmem->name); in tegra210_emc_table_device_init()
40 if (emc->nominal) { in tegra210_emc_table_device_init()
41 if (count != emc->num_timings) { in tegra210_emc_table_device_init()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
15 This driver is for the External Memory Controller (EMC) found on
16 Tegra20 chips. The EMC controls the external DRAM on the board.
25 This driver is for the External Memory Controller (EMC) found on
26 Tegra30 chips. The EMC controls the external DRAM on the board.
35 This driver is for the External Memory Controller (EMC) found on
36 Tegra124 chips. The EMC controls the external DRAM on the board.
45 tristate "NVIDIA Tegra210 External Memory Controller driver"
49 This driver is for the External Memory Controller (EMC) found on
50 Tegra210 chips. The EMC controls the external DRAM on the board.
Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
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Dtegra210-emc-cc-r21021.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument
53 * PTFV defines - basically just indexes into the per table PTFV array.
78 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] = \
79 next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] += \
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Dtegra210-emc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
891 /* nominal EMC frequency table */
893 /* derated EMC frequency table */
939 void (*set_clock)(struct tegra210_emc *emc, u32 clksrc);
940 u32 (*periodic_compensation)(struct tegra210_emc *emc);
943 static inline void emc_writel(struct tegra210_emc *emc, u32 value, in emc_writel() argument
946 writel_relaxed(value, emc->regs + offset); in emc_writel()
949 static inline u32 emc_readl(struct tegra210_emc *emc, unsigned int offset) in emc_readl() argument
951 return readl_relaxed(emc->regs + offset); in emc_readl()
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/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra210-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra210-emc
26 - description: external memory clock
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/linux-5.10/arch/arm64/boot/dts/nvidia/
Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
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Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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/linux-5.10/drivers/clk/tegra/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += clk.o
3 obj-y += clk-audio-sync.o
4 obj-y += clk-dfll.o
5 obj-y += clk-divider.o
6 obj-y += clk-periph.o
7 obj-y += clk-periph-fixed.o
8 obj-y += clk-periph-gate.o
9 obj-y += clk-pll.o
10 obj-y += clk-pll-out.o
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Dclk-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
23 #include "clk-id.h"
27 * banks present in the Tegra210 CAR IP block. The banks are
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
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Dclk-tegra-periph.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
781 * Critical for RAM re-repair operation, which must occur on resume
791 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
804 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),
877 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
881 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
885 data->periph.gate.regs = bank; in periph_clk_init()
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/linux-5.10/drivers/usb/host/
Dxhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/dma-mapping.h>
280 return readl(tegra->fpci_base + offset); in fpci_readl()
286 writel(value, tegra->fpci_base + offset); in fpci_writel()
291 return readl(tegra->ipfs_base + offset); in ipfs_readl()
297 writel(value, tegra->ipfs_base + offset); in ipfs_writel()
324 struct clk *clk = tegra->ss_src_clk; in tegra_xusb_set_ss_clk()
338 new_parent_rate = clk_get_rate(tegra->pll_u_480m); in tegra_xusb_set_ss_clk()
345 err = clk_set_parent(clk, tegra->pll_u_480m); in tegra_xusb_set_ss_clk()
361 err = clk_set_parent(clk, tegra->clk_m); in tegra_xusb_set_ss_clk()
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