1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
781 	 * Critical for RAM re-repair operation, which must occur on resume
791 	GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
804 	GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),
877 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);  in periph_clk_init()
881 		bank = get_reg_bank(data->periph.gate.clk_num);  in periph_clk_init()
885 		data->periph.gate.regs = bank;  in periph_clk_init()
903 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);  in gate_clk_init()
907 		clk = tegra_clk_register_periph_gate(data->name,  in gate_clk_init()
908 				data->p.parent_name, data->periph.gate.flags,  in gate_clk_init()
909 				clk_base, data->flags,  in gate_clk_init()
910 				data->periph.gate.clk_num,  in gate_clk_init()
928 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);  in div_clk_init()
932 		clk = tegra_clk_register_divider(data->name,  in div_clk_init()
933 				data->p.parent_name, clk_base + data->offset,  in div_clk_init()
934 				data->flags, data->periph.divider.flags,  in div_clk_init()
935 				data->periph.divider.shift,  in div_clk_init()
936 				data->periph.divider.width,  in div_clk_init()
937 				data->periph.divider.frac_width,  in div_clk_init()
938 				data->periph.divider.lock);  in div_clk_init()
965 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);  in init_pllp()
969 		clk = tegra_clk_register_divider(data->div_name, "pll_p",  in init_pllp()
970 				clk_base + data->offset, 0, data->div_flags,  in init_pllp()
971 				data->div_shift, 8, 1, data->lock);  in init_pllp()
972 		clk = tegra_clk_register_pll_out(data->pll_out_name,  in init_pllp()
973 				data->div_name, clk_base + data->offset,  in init_pllp()
974 				data->rst_shift + 1, data->rst_shift,  in init_pllp()
976 				data->lock);  in init_pllp()
984 		 * Tegra210 has control on enabling/disabling PLLP branches to  in init_pllp()
987 		 * re-parenting CPU off from "pll_p_out4" the PLLP branching to  in init_pllp()