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/qemu/docs/system/
H A Dtarget-mips.rst1 .. _MIPS-System-emulator:
3 MIPS System emulator
4 --------------------
6 Four executables cover simulation of 32 and 64-bit MIPS systems in both
7 endian options, ``qemu-system-mips``, ``qemu-system-mipsel``
8 ``qemu-system-mips64`` and ``qemu-system-mips64el``. Five different
11 - The MIPS Malta prototype board \"malta\"
13 - An ACER Pica \"pica61\". This machine needs the 64-bit emulator.
15 - MIPS emulator pseudo board \"mipssim\"
17 - A MIPS Magnum R4000 machine \"magnum\". This machine needs the
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/qemu/docs/system/arm/
H A Daspeed.rst1 …-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280…
6 Aspeed SoC : the AST2400 integrating an ARM926EJ-S CPU (400MHz), the
8 with dual cores ARM Cortex-A7 CPUs (1.2GHz).
15 - ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC
16 - ``quanta-q71l-bmc`` OpenBMC Quanta BMC
17 - ``supermicrox11-bmc`` Supermicro X11 BMC (ARM926EJ-S)
18 - ``supermicrox11spi-bmc`` Supermicro X11 SPI BMC (ARM1176)
22 - ``ast2500-evb`` Aspeed AST2500 Evaluation board
23 - ``romulus-bmc`` OpenPOWER Romulus POWER9 BMC
24 - ``witherspoon-bmc`` OpenPOWER Witherspoon POWER9 BMC
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H A Dstm32.rst1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…
4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by
7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html
9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are
12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller
14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are
17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller
19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L4
20 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series.
21 The following machines are based on this ARM Cortex-M4F chip :
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H A Dvexpress.rst1 Arm Versatile Express boards (``vexpress-a9``, ``vexpress-a15``)
7 - ``vexpress-a9`` models the combination of the Versatile Express
9 - ``vexpress-a15`` models the combination of the Versatile Express
17 - PL041 audio
18 - PL181 SD controller
19 - PL050 keyboard and mouse
20 - PL011 UARTs
21 - SP804 timers
22 - I2C controller
23 - PL031 RTC
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H A Dnuvoton.rst1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…
4 The `Nuvoton iBMC`_ chips are a family of Arm-based SoCs that are
7 NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
8 while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
12 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
14 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
17 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
19 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
22 - ``quanta-gbs-bmc`` Quanta GBS server BMC
23 - ``quanta-gsj`` Quanta GSJ server BMC
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H A Db-l475e-iot01a.rst1 B-L475E-IOT01A IoT Node (``b-l475e-iot01a``)
4 The B-L475E-IOT01A IoT Node uses the STM32L475VG SoC which is based on
5 ARM Cortex-M4F core. It is part of STMicroelectronics
6 :doc:`STM32 boards </system/arm/stm32>` and more specifically the STM32L4
7 ultra-low power series. The STM32L4x5 chip runs at up to 80 MHz and
8 integrates 128 KiB of SRAM and up to 1MiB of Flash. The B-L475E-IOT01A board
15 Currently B-L475E-IOT01A machines support the following devices:
17 - Cortex-M4F based STM32L4x5 SoC
18 - STM32L4x5 EXTI (Extended interrupts and events controller)
19 - STM32L4x5 SYSCFG (System configuration controller)
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H A Dsbsa.rst1 Arm Server Base System Architecture Reference board (``sbsa-ref``)
4 The ``sbsa-ref`` board intends to look like real hardware (while the ``virt``
9 - `Base System Architecture <https://developer.arm.com/documentation/den0094/>`__ (BSA)
10 - `Server Base System Architecture <https://developer.arm.com/documentation/den0029/>`__ (SBSA)
13 specification defines how the firmware reports that to any operating system.
21 The ``sbsa-ref`` board supports:
23 - A configurable number of AArch64 CPUs
24 - GIC version 3
25 - System bus AHCI controller
26 - System bus XHCI controller
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H A Dnrf.rst4 The `Nordic nRF`_ chips are a family of ARM-based System-on-Chip that
5 are designed to be used for low-power and short-range wireless solutions.
13 - ``microbit`` BBC micro:bit board with nRF51822 SoC
19 -----------------
21 * ARM Cortex-M0 (ARMv6-M)
23 * Clock controller
26 * GPIO controller
31 ---------------
34 * Real-Time Clock (RTC) controller
36 * SPI controller
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H A Dsabrelite.rst4 Boundary Devices SABRE Lite i.MX6 Development Board is a low-cost development
9 -----------------
13 * Up to 4 Cortex-A9 cores
14 * Generic Interrupt Controller
15 * 1 Clock Controller Module
16 * 1 System Reset Controller
21 * 1 FEC Ethernet controller
34 ------------
36 The SABRE Lite machine can start using the standard -kernel functionality
37 for loading a Linux kernel, U-Boot bootloader or ELF executable.
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H A Draspi.rst8 ARM1176JZF-S core, 512 MiB of RAM
10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
19 -------------------
21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU
22 * Interrupt controller
23 * DMA controller
24 * Clock and reset controller (CPRMAN)
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H A Dxlnx-zynq.rst1 Xilinx Zynq board (``xilinx-zynq-a9``)
4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
5 processing system (PS) and AMD programmable logic (PL) in a single device.
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
10 QEMU xilinx-zynq-a9 board supports following devices:
11 - A9 MPCORE
12 - cortex-a9
13 - GIC v1
14 - Generic timer
15 - wdt
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H A Dimx8mp-evk.rst1 NXP i.MX 8M Plus Evaluation Kit (``imx8mp-evk``)
4 The ``imx8mp-evk`` machine models the i.MX 8M Plus Evaluation Kit, based on an
8 -----------------
10 The ``imx8mp-evk`` machine implements the following devices:
12 * Up to 4 Cortex-A53 cores
13 * Generic Interrupt Controller (GICv3)
16 * 1 Designware PCI Express Controller
17 * 1 Ethernet Controller
24 * Secure Non-Volatile Storage (SNVS) including an RTC
28 ------------
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H A Dhighbank.rst4 ``highbank`` is a model of the Calxeda Highbank (ECX-1000) system,
5 which has four Cortex-A9 cores.
7 ``midway`` is a model of the Calxeda Midway (ECX-2000) system,
8 which has four Cortex-A15 cores.
12 - L2x0 cache controller
13 - SP804 dual timer
14 - PL011 UART
15 - PL061 GPIOs
16 - PL031 RTC
17 - PL022 synchronous serial port controller
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H A Dvirt.rst1 .. _arm-virt:
10 idiosyncrasies and limitations of a particular bit of real-world
18 ``virt-5.0`` machine type will behave like the ``virt`` machine from
19 the QEMU 5.0 release, and migration should work between ``virt-5.0``
20 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
22 the non-versioned ``virt`` machine type.
24 VM migration is not guaranteed when using ``-cpu max``, as features
33 - PCI/PCIe devices
34 - Flash memory
35 - Either one or two PL011 UARTs for the NonSecure World
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H A Dbananapi_m2u.rst1 Banana Pi BPI-M2U (``bpim2u``)
4 Banana Pi BPI-M2 Ultra is a quad-core mini single board computer built with
6 has onboard WiFi and BT. On the ports side, the BPI-M2 Ultra has 2 USB A
15 * SMP (Quad Core Cortex-A7)
16 * Generic Interrupt Controller configuration
18 * SDRAM controller
19 * Timer device (re-used from Allwinner A10)
21 * SD/MMC storage controller
35 - Graphical output via HDMI, GPU and/or the Display Engine
36 - Audio output
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/qemu/docs/system/ppc/
H A Dppce500.rst8 -----------------
14 * Multicore Programmable Interrupt Controller (MPIC) with MSI support
16 * 1 Freescale MPC8xxx I2C controller
18 * 1 Freescale MPC8xxx GPIO controller
19 * Power-off functionality via one GPIO pin
20 * 1 Freescale MPC8xxx PCI host controller
22 * 1 Freescale Enhanced Secure Digital Host controller (eSDHC)
23 * 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC)
26 ----------------------------------
29 which it passes to the guest, if there is no ``-dtb`` option. This provides
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H A Dpowernv.rst4 PowerNV (as Non-Virtualized) is the "bare metal" platform using the
9 The PowerNV QEMU machine tries to emulate a PowerNV system at the
12 does low level system initialization, like DRAM training. This is
16 -----------------
20 * Simple LPC Controller.
21 * Processor Service Interface (PSI) Controller.
22 * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
24 * Simple OCC is an on-chip micro-controller used for power management tasks.
30 ---------------
37 * NX controller.
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/qemu/docs/system/devices/
H A Dcan.rst4 emulated CAN controller chips together by one or multiple CAN buses
5 (the controller device "canbus" parameter). The individual buses
6 can be connected to host system CAN API (at this time only Linux
12 The initial submission implemented SJA1000 controller which
20 In 2020, CTU CAN FD controller model has been added as part
21 of the bachelor thesis of Jan Charvat. This controller is complete
22 open-source/design/hardware solution. The core designer
34 ----------------------------------------------------------
38 (1) CAN bus Kvaser PCI CAN-S (single SJA1000 channel) board. QEMU startup options::
40 -object can-bus,id=canbus0
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H A Dusb.rst2 -------------
4 QEMU can emulate a PCI UHCI, OHCI, EHCI or XHCI USB controller. You can
12 XHCI controller support
16 more virtualization-friendly when compared to EHCI and UHCI, thus XHCI
18 supports XHCI (which should be the case for any operating system
21 |qemu_system| -device qemu-xhci
24 only controller you need. With only a single USB controller (and
25 therefore only a single USB bus) present in the system there is no
29 EHCI controller support
34 devices. The companion controller setup is more convenient to use
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/qemu/docs/system/riscv/
H A Dvirt.rst8 real-world hardware.
11 -----------------
17 * Platform-Level Interrupt Controller (PLIC)
22 * 8 virtio-mmio transport devices
31 ----------------------------------
34 which it passes to the guest, if there is no ``-dtb`` option. This provides
36 the various devices in the system. Guest software should discover the devices
39 If users want to provide their own DTB, they can use the ``-dtb`` option.
42 * The number of subnodes of the /cpus node should match QEMU's ``-smp`` option
43 * The /memory reg size should match QEMU’s selected ram_size via ``-m``
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H A Dsifive_u.rst4 SiFive HiFive Unleashed Development Board is the ultimate RISC-V development
5 board featuring the Freedom U540 multi-core RISC-V processor.
8 -----------------
15 * Platform-Level Interrupt Controller (PLIC)
17 * L2 Loosely Integrated Memory (L2-LIM)
18 * DDR memory controller
20 * 1 GEM Ethernet controller
21 * 1 GPIO controller
22 * 1 One-Time Programmable (OTP) memory with stored serial number
23 * 1 DMA controller
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H A Dmicrochip-icicle-kit.rst1 Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
5 SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
8 https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpgas/polarfire-soc-fpgas
11 https://www.microchip.com/en-us/development-tool/mpfs-icicle-kit-es
14 -----------------
16 The ``microchip-icicle-kit`` machine supports the following devices:
21 * Platform-Level Interrupt Controller (PLIC)
22 * L2 Loosely Integrated Memory (L2-LIM)
23 * DDR memory controller
25 * 1 DMA controller
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/qemu/include/hw/sd/
H A Dsdhci.h2 * SD Association Host Standard Specification v2.0 controller emulation
8 * Based on MMC controller for Samsung S5PC1xx-based board emulation
33 /* SD/MMC host controller state */
54 uint32_t sdmasysad; /* SDMA System Address register */
60 uint32_t rspreg[4]; /* Response Registers 0-3 */
77 uint64_t admasysaddr; /* ADMA System Address Register */
80 /* Read-only registers */
83 uint16_t version; /* Host Controller Version Register */
90 /* Buffer Data Port Register - virtual access point to R and W buffers */
91 /* Software Reset Register - always reads as 0 */
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/qemu/include/hw/mem/
H A Dnpcm7xx_mc.h2 * Nuvoton NPCM7xx Memory Controller stub
19 #include "system/memory.h"
23 * struct NPCM7xxMCState - Device state for the memory controller.
24 * @parent: System bus device.
33 #define TYPE_NPCM7XX_MC "npcm7xx-mc"
/qemu/hw/arm/
H A Dversatilepb.c2 * ARM Versatile Platform/Application Baseboard System emulation.
4 * Copyright (c) 2005-2007 CodeSourcery.
17 #include "system/system.h"
24 #include "qemu/error-report.h"
29 #include "target/arm/cpu-qom.h"
36 /* Primary interrupt controller. */
68 flags = s->level & s->mask; in vpb_sic_update()
69 qemu_set_irq(s->parent[s->irq], flags != 0); in vpb_sic_update()
79 if (!(s->pic_enable & mask)) in vpb_sic_update_pic()
81 qemu_set_irq(s->parent[i], (s->level & mask) != 0); in vpb_sic_update_pic()
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