| /qemu/target/hexagon/imported/ |
| H A D | ldst.idef | 19 * Load and Store instruction definitions
103 /* The set of addressing modes standard to all Store instructions */
115 /* The set of 32-bit store instructions */
116 STD_ST_AMODES(storerb, "Rt32", "memb","Store Byte",ATTRIBS(A_MEMSIZE_1B,A_STORE),"0",fSTORE(1,1,EA,…
117 STD_ST_AMODES(storerh, "Rt32", "memh","Store Half integer",ATTRIBS(A_REGWRSIZE_2B,A_MEMSIZE_2B,A_ST…
118 STD_ST_AMODES(storerf, "Rt.H32", "memh","Store Upper Half integer",ATTRIBS(A_REGWRSIZE_2B,A_MEMSIZE…
119 STD_ST_AMODES(storeri, "Rt32", "memw","Store Word",ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_STORE),"2"…
120 STD_ST_AMODES(storerd, "Rtt32","memd","Store Double integer",ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_…
121 STD_ST_AMODES(storerinew, "Nt8.new", "memw","Store Word",ATTRIBS(A_REGWRSIZE_4B,A_NOTE_NEWVAL_SLOT0…
122 STD_ST_AMODES(storerbnew, "Nt8.new", "memb","Store Byte",ATTRIBS(A_NOTE_NEWVAL_SLOT0,A_NVSTORE,A_NO…
[all …]
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| H A D | subinsns.idef | 137 …16+#u4:2)=Rt16", ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_STORE,A_SUBINSN), "store word", {fEA_RI(RsV…
138 Q6INSN(SS1_storeb_io, "memb(Rs16+#u4:0)=Rt16", ATTRIBS(A_MEMSIZE_1B,A_STORE,A_SUBINSN), "store byt…
139 Q6INSN(SS2_storeh_io, "memh(Rs16+#u3:1)=Rt16", ATTRIBS(A_MEMSIZE_2B,A_STORE,A_SUBINSN), "store hal…
140 …29+#s6:3)=Rtt8", ATTRIBS(A_REGWRSIZE_8B,A_MEMSIZE_8B,A_STORE,A_SUBINSN), "store dword",{fEA_RI(fRE…
141 …9+#u5:2)=Rt16", ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_STORE,A_SUBINSN), "store word", {fEA_RI(fRE…
142 …2)=#0", ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_STORE,A_SUBINSN,A_ROPS_2), "store word", {fEA_RI(RsV…
143 …"memb(Rs16+#u4:0)=#0", ATTRIBS(A_MEMSIZE_1B,A_STORE,A_SUBINSN,A_ROPS_2), "store byte", {fEA_RI(RsV…
144 …2)=#1", ATTRIBS(A_REGWRSIZE_4B,A_MEMSIZE_4B,A_STORE,A_SUBINSN,A_ROPS_2), "store word", {fEA_RI(RsV…
145 …"memb(Rs16+#u4:0)=#1", ATTRIBS(A_MEMSIZE_1B,A_STORE,A_SUBINSN,A_ROPS_2), "store byte", {fEA_RI(RsV…
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| /qemu/accel/tcg/ |
| H A D | ldst_atomicity.c.inc | 2 * Routines common to user and system emulation of load/store.
13 #include "host/store-insert-al16.h.inc"
594 * @val: value to store
596 * Atomically store 2 aligned bytes to @pv.
607 * @val: value to store
609 * Atomically store 4 aligned bytes to @pv.
620 * @val: value to store
622 * Atomically store 8 aligned bytes to @pv.
662 * @val: shifted value to store
663 * @msk: mask for value to store
[all …]
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| /qemu/target/s390x/ |
| H A D | cpu_features_def.h.inc | 29 DEF_FEAT(STFLE, "stfle", STFL, 7, "Store-facility-list-extended facility")
47 DEF_FEAT(STORE_CLOCK_FAST, "stckf", STFL, 25, "Store-clock-fast facility")
53 DEF_FEAT(COMPARE_AND_SWAP_AND_STORE, "csst", STFL, 32, "Compare-and-swap-and-store facility")
54 DEF_FEAT(COMPARE_AND_SWAP_AND_STORE_2, "csst2", STFL, 33, "Compare-and-swap-and-store facility 2")
85 DEF_FEAT(STORE_HYPERVISOR_INFO, "sthyi", STFL, 74, "Store-hypervisor-information facility")
86 DEF_FEAT(ACCESS_EXCEPTION_FS_INDICATION, "aefsi", STFL, 75, "Access-exception-fetch/store-indicatio…
172 DEF_FEAT(PLO_CSST, "plo-csst", PLO, 12, "PLO Compare and swap and store (32 bit in general register…
173 DEF_FEAT(PLO_CSSTG, "plo-csstg", PLO, 13, "PLO Compare and swap and store (64 bit in parameter list…
174 DEF_FEAT(PLO_CSSTGR, "plo-csstgr", PLO, 14, "PLO Compare and swap and store (64 bit in general regi…
175 DEF_FEAT(PLO_CSSTX, "plo-csstx", PLO, 15, "PLO Compare and swap and store (128 bit in parameter lis…
[all …]
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| /qemu/tests/tcg/hexagon/ |
| H A D | mem_noshuf_exception.c | 22 * That the load will get the data from the store if the addresses overlap.
23 * To accomplish this, we perform the store first. However, we have to
24 * handle the case where the store raises an exception. In that case, the
25 * store should not alter the machine state.
27 * We test this with a mem_noshuf packet with a store to a global variable,
32 * raise an exception and allows the store to happen.
98 * raise an exception and allows the store to happen. in main()
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| /qemu/host/include/aarch64/host/ |
| H A D | store-insert-al16.h.inc | 3 * Atomic store insert into 128-bit, AArch64 version.
14 * @val: shifted value to store
15 * @msk: mask for value to store
17 * Atomically store @val to @p masked by @msk.
25 * arithmetic into the load-exclusive/store-conditional pair.
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| /qemu/docs/specs/ |
| H A D | acpi_cpu_hotplug.rst | 114 registers will read/store data from/to selected CPU.
200 #. Store 0x0 to the 'CPU selector' register, attempting to switch to modern mode
201 #. Store 0x0 to the 'CPU selector' register, to ensure valid selector value
202 #. Store 0x0 to the 'Command field' register
210 #. Store 0x0 to the 'CPU selector' register.
211 #. Store 0x0 to the 'Command field' register.
223 #. Store 0x0 to the 'CPU selector' register, to ensure that it's in
225 #. Store 0x0 to the 'Command field' register to make 'Command data'
230 #. Store the iterator to the 'CPU selector' register.
233 #. Otherwise store 0x0 to the 'CPU selector' register, to put it
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| /qemu/target/hexagon/ |
| H A D | attribs_def.h.inc | 38 /* Load and Store attributes */
40 DEF_ATTRIB(STORE, "Stores to memory", "", "")
48 DEF_ATTRIB(SCALAR_STORE, "Store is scalar", "", "")
58 DEF_ATTRIB(RLS_INNER, "Store release inner visibility", "", "")
59 DEF_ATTRIB(RLS_ALL_THREAD, "Store release among all threads", "", "")
60 DEF_ATTRIB(RLS_SAME_THREAD, "Store release with the same thread", "", "")
81 DEF_ATTRIB(CVI_SCATTER_RELEASE, "CVI Store Release for scatter", "", "")
96 DEF_ATTRIB(NVSTORE, "New-value store", "", "")
173 DEF_ATTRIB(RESTRICT_NOSLOT1_STORE, "Packet must not have slot 1 store", "", "")
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| /qemu/host/include/generic/host/ |
| H A D | store-insert-al16.h.inc | 3 * Atomic store insert into 128-bit, generic version.
14 * @val: shifted value to store
15 * @msk: mask for value to store
17 * Atomically store @val to @p masked by @msk.
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| /qemu/tests/tcg/multiarch/ |
| H A D | test-plugin-mem-access.c | 8 * 8,16,32 load/store are tested for all arch.
9 * 64,128 load/store are tested for aarch64/x64.
26 /* ,store_u8,.*,8,store,0xf1 */
38 PRINT_EXPECTED(store_##name, type, #value, "store"); \
52 PRINT_EXPECTED(atomic_op_##name, type, #value, "store"); \
93 "0xf122334455667788f123456789abcdef", "store"); in print_expected_store_u128()
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| /qemu/include/migration/ |
| H A D | snapshot.h | 25 * @vmstate: blockdev node name to store VM state in
30 * On failure, store an error through @errp and return %false.
45 * On failure, store an error through @errp and return %false.
59 * On failure, store an error through @errp and return %false.
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| /qemu/target/arm/tcg/ |
| H A D | neon-ls.decode | 1 # AArch32 Neon load/store instruction descriptions
22 # Encodings for Neon load/store instructions where the T32 encoding
33 # Neon load/store multiple structures
43 # Neon load/store single structure to one lane
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| H A D | sme-fa64.decode | 49 FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structure load/store
56 # --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers
58 # --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm)
59 # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
60 # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
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| /qemu/include/qom/ |
| H A D | object_interfaces.h | 53 * @errp: if an error occurs, a pointer to an area to store the error
78 * @errp: if an error occurs, a pointer to an area to store the error
93 * @errp: if an error occurs, a pointer to an area to store the error
103 * @errp: if an error occurs, a pointer to an area to store the error
118 * @errp: if an error occurs, a pointer to an area to store the error
163 * @errp: if an error occurs, a pointer to an area to store the error
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| /qemu/docs/devel/ |
| H A D | multi-thread-tcg.rst | 255 ordered hosts needs to ensure things like store-after-load re-ordering
279 This would enforce a strong load/store ordering so all loads/stores
287 special variants of load/store instructions that imply acquire/release
303 strongest form before any load/store operations. The solution was
329 some sort of test and conditional store will be truly atomic w.r.t.
333 The second type offer a pair of load/store instructions which offer a
335 load and store instructions. An example of this is Arm's ldrex/strex
337 successful store only if no other CPU has accessed the memory region
348 - Support load/store exclusive (or load link/store conditional) pairs
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| H A D | loads-stores.rst | 6 Load and Store APIs
29 store: ``st{size}_{endian}_p(ptr, val)``
60 store: ``stn{endian}_p(ptr, sz, val)``
110 store: ``cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr)``
139 store: ``cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmuidx, retaddr)``
177 store: ``cpu_st{size}{end}_data_ra(env, ptr, val, ra)``
216 store: ``cpu_st{size}{end}_data(env, ptr, val)``
315 store: ``helper_{size}_mmu(env, addr, val, opindex, retaddr)``
421 ``store: st{size}_{endian}_phys``
521 ``store: st{size}_{endian}_pci_dma``
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| H A D | atomics.rst | 125 components of the system, before all the LOAD or STORE operations
129 components of the system, after all the LOAD or STORE operations
145 before all the LOAD or STORE operations specified afterwards.
149 - ``qatomic_store_release()``, which guarantees the STORE to appear to
151 after all the LOAD or STORE operations specified before.
170 - ``smp_wmb()`` guarantees that all the STORE operations specified before
171 the barrier will appear to happen before all the STORE operations
179 the barrier will appear to happen before all the LOAD or STORE operations
183 - ``smp_mb_release()`` guarantees that all the STORE operations specified *after*
184 the barrier will appear to happen after all the LOAD or STORE operations
[all …]
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| /qemu/util/ |
| H A D | cutils.c | 421 * Convert string @nptr to an integer, and store it in @result.
429 * If no conversion is performed, store @nptr in *@endptr, 0 in
437 * If the conversion overflows @result, store INT_MAX in @result,
440 * If the conversion underflows @result, store INT_MIN in @result,
443 * Else store the converted value in @result, and return zero.
478 * Convert string @nptr to an unsigned integer, and store it in @result.
486 * If no conversion is performed, store @nptr in *@endptr, 0 in
494 * If the conversion overflows @result, store UINT_MAX in @result,
497 * Else store the converted value in @result, and return zero.
549 * Convert string @nptr to a long integer, and store it in @result.
[all …]
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| /qemu/target/hppa/ |
| H A D | op_helper.c | 113 /* The 3 byte store must appear atomic. */ in do_stby_b()
138 /* The 3 byte store must appear atomic. */ in do_stdby_b()
150 /* The 5 byte store must appear atomic. */ in do_stdby_b()
159 /* The 6 byte store must appear atomic. */ in do_stdby_b()
168 /* The 7 byte store must appear atomic. */ in do_stdby_b()
210 /* The 3 byte store must appear atomic. */ in do_stby_e()
237 /* The 7 byte store must appear atomic. */ in do_stdby_e()
248 /* The 6 byte store must appear atomic. */ in do_stdby_e()
258 /* The 5 byte store must appear atomic. */ in do_stdby_e()
271 /* The 3 byte store must appear atomic. */ in do_stdby_e()
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| /qemu/qapi/ |
| H A D | uefi.json | 6 # = UEFI Variable Store
8 # The QEMU efi variable store implementation (hw/uefi/) uses this to
9 # store non-volatile variables in json format on disk.
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| /qemu/tests/qemu-iotests/ |
| H A D | 267.out | 9 Error: no block device can store vmstate for snapshot
11 no block device can store vmstate for snapshot
13 Error: no block device can store vmstate for snapshot
25 no block device can store vmstate for snapshot
61 no block device can store vmstate for snapshot
86 no block device can store vmstate for snapshot
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| /qemu/target/sparc/ |
| H A D | asi.h | 165 #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
202 #define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
242 #define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
285 #define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */
286 #define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */
288 #define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
291 #define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load,
297 #define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load,
301 #define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load,
307 #define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load,
[all …]
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| /qemu/linux-user/include/host/riscv/ |
| H A D | host-signal.h | 35 * Detect store by reading the instruction at the program counter. in host_signal_write()
55 case 0x23: /* store */ in host_signal_write()
56 case 0x27: /* store-fp */ in host_signal_write()
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| /qemu/target/ppc/translate/ |
| H A D | fixedpoint-impl.c.inc | 21 * Fixed-Point Load/Store Instructions
25 bool store, MemOp mop)
29 if (update && (ra == 0 || (!store && ra == rt))) {
37 if (store) {
48 static bool do_ldst_D(DisasContext *ctx, arg_D *a, bool update, bool store,
51 return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
55 bool store, MemOp mop)
61 return do_ldst_D(ctx, &d, update, store, mop);
65 bool store, MemOp mop)
67 return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
[all …]
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| /qemu/include/qapi/ |
| H A D | visitor.h | 285 * On failure, set *@obj to NULL and store an error through @errp.
305 * On failure, store an error through @errp. Can happen only when @v
344 * On failure, set *@list to NULL and store an error through @errp.
381 * On failure, store an error through @errp. Can happen only when @v
416 * the qtype of the next thing to be visited, and store it in
419 * On failure, set *@obj to NULL and store an error through @errp.
512 * On failure, store an error through @errp. Can happen only when @v
546 * On failure, store an error through @errp. Can happen only when @v
627 * On failure, store an error through @errp. Can happen only when @v
648 * On failure, set *@obj to NULL and store an error through @errp.
[all …]
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