/linux-5.10/Documentation/devicetree/bindings/clock/ ! |
D | st,stm32mp1-rcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/st,stm32mp1-rcc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Gabriel Fernandez <gabriel.fernandez@st.com> 13 The RCC IP is both a reset and a clock controller. 14 RCC makes also power management (resume/supend and wakeup interrupt). 18 Documentation/devicetree/bindings/clock/clock-bindings.txt 24 dt-bindings/clock/stm32mp1-clks.h header and can be used in device 33 The index is the bit number within the RCC registers bank, starting from RCC [all …]
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/linux-5.10/Documentation/devicetree/bindings/net/ ! |
D | stm32-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#" 6 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 11 - Alexandre Torgue <alexandre.torgue@st.com> 12 - Christophe Roullier <christophe.roullier@st.com> 23 - st,stm32-dwmac 24 - st,stm32mp1-dwmac 26 - compatible 29 - $ref: "snps,dwmac.yaml#" [all …]
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/linux-5.10/Documentation/devicetree/bindings/rtc/ ! |
D | st,stm32-rtc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/rtc/st,stm32-rtc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Gabriel Fernandez <gabriel.fernandez@st.com> 15 - st,stm32-rtc 16 - st,stm32h7-rtc 17 - st,stm32mp1-rtc 26 clock-names: 28 - const: pclk [all …]
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/linux-5.10/arch/arm/boot/dts/ ! |
D | stm32mp151.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/stm32mp1-clks.h> 8 #include <dt-bindings/reset/stm32mp1-resets.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 15 #address-cells = <1>; 16 #size-cells = <0>; 19 compatible = "arm,cortex-a7"; [all …]
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D | stm32mp15xc.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved 10 compatible = "st,stm32mp1-cryp"; 13 clocks = <&rcc CRYP1>; 14 resets = <&rcc CRYP1_R>;
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/linux-5.10/Documentation/devicetree/bindings/i2c/ ! |
D | st,stm32-i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Pierre-Yves MORDRET <pierre-yves.mordret@st.com> 13 - $ref: /schemas/i2c/i2c-controller.yaml# 14 - if: 19 - st,stm32f7-i2c 20 - st,stm32mp15-i2c 23 i2c-scl-rising-time-ns: [all …]
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/linux-5.10/Documentation/devicetree/bindings/remoteproc/ ! |
D | st,stm32-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: "http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#" 5 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 14 - Fabien Dessenne <fabien.dessenne@st.com> 15 - Arnaud Pouliquen <arnaud.pouliquen@st.com> 19 const: st,stm32mp1-m4 30 st,syscfg-holdboot: 32 - Phandle of syscon block. 33 - The offset of the hold boot setting register. [all …]
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/linux-5.10/Documentation/devicetree/bindings/crypto/ ! |
D | st,stm32-cryp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/crypto/st,stm32-cryp.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lionel Debieve <lionel.debieve@st.com> 15 - st,stm32f756-cryp 16 - st,stm32mp1-cryp 31 - compatible 32 - reg 33 - clocks [all …]
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D | st,stm32-hash.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/crypto/st,stm32-hash.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lionel Debieve <lionel.debieve@st.com> 15 - st,stm32f456-hash 16 - st,stm32f756-hash 33 dma-names: 35 - const: in 37 dma-maxburst: [all …]
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D | st,stm32-crc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/crypto/st,stm32-crc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lionel Debieve <lionel.debieve@st.com> 14 const: st,stm32f7-crc 23 - compatible 24 - reg 25 - clocks 30 - | [all …]
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/linux-5.10/Documentation/devicetree/bindings/iio/adc/ ! |
D | st,stm32-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#" 5 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 10 STM32 ADC is a successive approximation analog-to-digital converter. 13 stored in a left-aligned or right-aligned 32-bit data register. 17 voltage goes beyond the user-defined, higher or lower thresholds. 22 - Fabrice Gasnier <fabrice.gasnier@st.com> 27 - st,stm32f4-adc-core 28 - st,stm32h7-adc-core [all …]
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D | st,stm32-dfsdm-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Fabrice Gasnier <fabrice.gasnier@st.com> 11 - Olivier Moysan <olivier.moysan@st.com> 14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to 17 - Sigma delta modulators (motor control, metering...) 18 - PDM microphones (audio digital microphone) 21 up to 4 filters on stm32h7 or 6 filters on stm32mp1. [all …]
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/linux-5.10/Documentation/devicetree/bindings/watchdog/ ! |
D | st,stm32-iwdg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/watchdog/st,stm32-iwdg.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Yannick Fertre <yannick.fertre@st.com> 11 - Christophe Roullier <christophe.roullier@st.com> 14 - $ref: "watchdog.yaml#" 19 - st,stm32-iwdg 20 - st,stm32mp1-iwdg 27 - description: Low speed clock [all …]
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/linux-5.10/Documentation/devicetree/bindings/reset/ ! |
D | st,stm32mp1-rcc.txt | 1 STMicroelectronics STM32MP1 Peripheral Reset Controller 4 The RCC IP is both a reset and a clock controller. 6 Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
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/linux-5.10/Documentation/devicetree/bindings/mtd/ ! |
D | st,stm32-fmc2-nand.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Christophe Kerello <christophe.kerello@st.com> 15 - st,stm32mp15-fmc2 16 - st,stm32mp1-fmc2-nfc 27 - description: tx DMA channel 28 - description: rx DMA channel 29 - description: ecc DMA channel [all …]
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/linux-5.10/Documentation/devicetree/bindings/display/ ! |
D | st,stm32-dsi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Philippe Cornu <philippe.cornu@st.com> 11 - Yannick Fertre <yannick.fertre@st.com> 14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller. 17 - $ref: dsi-controller.yaml# 21 const: st,stm32-dsi 28 - description: Module Clock [all …]
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D | st,stm32-ltdc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/st,stm32-ltdc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics STM32 lcd-tft display controller 10 - Philippe Cornu <philippe.cornu@st.com> 11 - Yannick Fertre <yannick.fertre@st.com> 15 const: st,stm32-ltdc 22 - description: events interrupt line. 23 - description: errors interrupt line. [all …]
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/linux-5.10/Documentation/devicetree/bindings/media/ ! |
D | st,stm32-dcmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/st,stm32-dcmi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Hugues Fruchet <hugues.fruchet@st.com> 14 const: st,stm32-dcmi 25 clock-names: 27 - const: mclk 32 dma-names: 34 - const: tx [all …]
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/linux-5.10/Documentation/devicetree/bindings/spi/ ! |
D | st,stm32-qspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/st,stm32-qspi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Christophe Kerello <christophe.kerello@st.com> 11 - Patrice Chotard <patrice.chotard@st.com> 14 - $ref: "spi-controller.yaml#" 18 const: st,stm32f469-qspi 22 - description: registers 23 - description: memory mapping [all …]
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D | st,stm32-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 the Serial Peripheral Interface. It supports full-duplex, half-duplex and 13 from 4 to 32-bit data size. 16 - Erwan Leray <erwan.leray@st.com> 17 - Fabrice Gasnier <fabrice.gasnier@st.com> 20 - $ref: "spi-controller.yaml#" 21 - if: [all …]
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/linux-5.10/Documentation/devicetree/bindings/sound/ ! |
D | st,stm32-i2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/st,stm32-i2s.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Olivier Moysan <olivier.moysan@st.com> 19 - st,stm32h7-i2s 21 "#sound-dai-cells": 29 - description: clock feeding the peripheral bus interface. 30 - description: clock feeding the internal clock generator. 31 - description: I2S parent clock for sampling rates multiple of 8kHz. [all …]
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/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ ! |
D | st,stm32-fmc2-ebi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped 14 - to translate AXI transactions into the appropriate external device 16 - to meet the access time requirements of the external devices 22 - Christophe Kerello <christophe.kerello@st.com> 26 const: st,stm32mp1-fmc2-ebi 37 "#address-cells": [all …]
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/linux-5.10/Documentation/devicetree/bindings/dma/ ! |
D | st,stm32-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 The STM32 DMA is a general-purpose direct memory access controller capable of 13 described in the dma.txt file, using a four-cell specifier for each 19 -bit 9: Peripheral Increment Address 22 -bit 10: Memory Increment Address 25 -bit 15: Peripheral Increment Offset Size 27 0x1: offset size is fixed to 4 (32-bit alignment) [all …]
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/linux-5.10/drivers/reset/ ! |
D | reset-stm32mp1.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 12 #include <linux/reset-controller.h> 36 addr = data->membase + (bank * reg_width); in stm32_reset_update() 66 reg = readl(data->membase + (bank * reg_width)); in stm32_reset_status() 78 { .compatible = "st,stm32mp1-rcc"}, 84 struct device *dev = &pdev->dev; in stm32_reset_probe() 91 return -ENOMEM; in stm32_reset_probe() 98 data->membase = membase; in stm32_reset_probe() 99 data->rcdev.owner = THIS_MODULE; in stm32_reset_probe() [all …]
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/linux-5.10/Documentation/devicetree/bindings/hwlock/ ! |
D | st,stm32-hwspinlock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/hwlock/st,stm32-hwspinlock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Benjamin Gaignard <benjamin.gaignard@st.com> 11 - Fabien Dessenne <fabien.dessenne@st.com> 14 "#hwlock-cells": 18 const: st,stm32-hwspinlock 26 clock-names: 28 - const: hsem [all …]
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