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/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC SROM Controller driver
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The SROM controller can be used to attach external peripherals. In this case
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
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/linux-5.10/drivers/memory/samsung/
Dexynos-srom.c1 // SPDX-License-Identifier: GPL-2.0
6 // Exynos - SROM Controller support
17 #include "exynos-srom.h"
20 /* SROM side */
29 * struct exynos_srom_reg_dump: register dump of SROM Controller registers.
30 * @offset: srom register offset from the controller base address.
39 * struct exynos_srom: platform data for exynos srom controller driver.
41 * @reg_base: srom base address
67 static int exynos_srom_configure_bank(struct exynos_srom *srom, in exynos_srom_configure_bank() argument
75 return -EINVAL; in exynos_srom_configure_bank()
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/linux-5.10/arch/arm/boot/dts/
Dexynos5410-smdk5410.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/irq.h>
22 stdout-path = "serial2:115200n8";
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 clock-output-names = "fin_pll";
29 #clock-cells = <0>;
32 pmic_ap_clk: pmic-ap-clk {
34 compatible = "fixed-clock";
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/linux-5.10/drivers/net/ethernet/dec/tulip/
Dde4x5.h16 #define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */
17 #define DE4X5_TPD iobase+(0x008 << lp->bus) /* Transmit Poll Demand Reg */
18 #define DE4X5_RPD iobase+(0x010 << lp->bus) /* Receive Poll Demand Reg */
19 #define DE4X5_RRBA iobase+(0x018 << lp->bus) /* RX Ring Base Address Reg */
20 #define DE4X5_TRBA iobase+(0x020 << lp->bus) /* TX Ring Base Address Reg */
21 #define DE4X5_STS iobase+(0x028 << lp->bus) /* Status Register */
22 #define DE4X5_OMR iobase+(0x030 << lp->bus) /* Operation Mode Register */
23 #define DE4X5_IMR iobase+(0x038 << lp->bus) /* Interrupt Mask Register */
24 #define DE4X5_MFC iobase+(0x040 << lp->bus) /* Missed Frame Counter */
25 #define DE4X5_APROM iobase+(0x048 << lp->bus) /* Ethernet Address PROM */
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Dde4x5.c41 Digital Semiconductor SROM Specification. The driver currently
44 DC21040 (no SROM)
56 SMC9332 (w/new SROM)
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
72 measurement. Their error is +/-20k on a quiet (private) network and also
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
159 I have added SROM decoding routines to make this driver work with any
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/linux-5.10/drivers/net/ethernet/davicom/
Ddm9000.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * (C) Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
40 /* Board/System/Debug information/definition ---------------- */
58 MODULE_PARM_DESC(debug, "dm9000 debug level (0-6)");
88 /* Structure/enum declaration ------------------------------- */
142 dev_dbg(db->dev, msg); \
151 /* DM9000 network board routine ---------------------------- */
159 writeb(reg, db->io_addr); in ior()
160 return readb(db->io_data); in ior()
170 writeb(reg, db->io_addr); in iow()
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/linux-5.10/drivers/net/ethernet/apple/
Dbmac.c1 // SPDX-License-Identifier: GPL-2.0-only
31 #include <asm/page.h>
39 #define trunc_page(x) ((void *)(((unsigned long)(x)) & ~((unsigned long)(PAGE_SIZE - 1))))
40 #define round_page(x) trunc_page(((unsigned long)(x)) + ((unsigned long)(PAGE_SIZE - 1)))
181 dbdma_st32(&dmap->control, in dbdma_continue()
189 dbdma_st32(&dmap->control, in dbdma_reset()
192 while (dbdma_ld32(&dmap->status) & RUN) in dbdma_reset()
201 out_le16(&cp->command, cmd); in dbdma_setcmd()
202 out_le16(&cp->req_count, count); in dbdma_setcmd()
203 out_le32(&cp->phy_addr, addr); in dbdma_setcmd()
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/linux-5.10/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.c3 * Copyright (c) 2013 Hauke Mehrtens <hauke@hauke-m.de>
50 /* n-mode support capability */
82 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
133 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
167 #define BRCMS_PLCP_AUTO -1
172 #define BRCMS_PROTECTION_AUTO -1
199 /* MSC in use,indicates b0-6 holds an mcs */
203 /* stf mode mask: siso, cdd, stbc, sdm */
205 /* stf mode shift */
209 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
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