Lines Matching +full:srom +full:- +full:page +full:- +full:mode
41 Digital Semiconductor SROM Specification. The driver currently
44 DC21040 (no SROM)
56 SMC9332 (w/new SROM)
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
72 measurement. Their error is +/-20k on a quiet (private) network and also
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
165 (with the latest SROM complying with the SROM spec V3: their first was
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
196 autonegotiation feature in the SROM autoconf code, this detection will
201 and media. The only lexical constraints are: the board name (dev->name)
208 sub-parameters:
211 Case sensitivity is important for the sub-parameters. They *must* be
224 correct in relation to what the adapter SROM says it has. There's no way
234 insmod "args" line; for built-in kernels either change the driver to do
239 ------
242 ----------------
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
283 Add new autosense algorithms for media/mode
285 Re-formatted.
290 checking is done now - assume BIOS is good!
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
298 0.42 26-Apr-96 Fix MII write TA bit error.
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
308 Fix TX under-run bug for non DC21140 chips.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
329 0.5 30-Jan-97 Added SROM decoding functions.
333 Added multi-MAC, one SROM feature from discussion
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
343 Fix initialisation problem with lp->timeout in
347 0.52 26-Apr-97 Some changes may not credit the right people -
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
361 Fix multi-MAC, one SROM, to work with 2114x chips:
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
389 case where a 21140 under SROM control uses, e.g. AUI
395 when using SROM control from problem report by
404 lp->rst not run because lp->ibn not initialised -
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
420 Change dev->interrupt to lp->interrupt to ensure
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
428 0.545 28-Nov-99 Further Moto SROM bug fix from
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
442 <maz@wild-wind.fr.eu.org>
466 #include <linux/dma-mapping.h>
493 int ta; /* One cycle TA time - 802.3u is confusing here */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
516 u_int ttm; /* Transmit Threshold Mode for each media */
524 u_char ext; /* csr13-15 valid when set */
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
554 ** Define special SROM detection cases
565 ** SROM Repair definitions. If a broken SROM is detected a card may
659 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
682 imr |= lp->irq_en;\
688 imr &= ~lp->irq_en;\
693 imr |= lp->irq_mask;\
699 imr &= ~lp->irq_mask;\
729 ** SROM Structure
810 int media; /* Media (eg TP), mode (eg 100B)*/
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
836 struct sk_buff_head queue; /* Save the (re-ordered) skb's */
838 struct de4x5_srom srom; /* A copy of the SROM */ member
841 bool useSROM; /* For non-DEC card use SROM */
846 int defMedium; /* SROM default medium */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
863 ** To get around certain poxy cards that don't provide an SROM
865 ** chip's address. I'll assume there's not a bad SROM iff:
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
986 static char *build_setup_frame(struct net_device *dev, int mode);
1012 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1025 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1030 ** List the SROM infoleaf functions and chipsets
1045 ** List the SROM info block functions
1057 #define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1104 if (lp->bus == EISA) { in de4x5_hw_init()
1115 return -ENXIO; /* Hardware could not reset */ in de4x5_hw_init()
1121 lp->useSROM = false; in de4x5_hw_init()
1122 if (lp->bus == PCI) { in de4x5_hw_init()
1129 return -ENXIO; in de4x5_hw_init()
1132 dev->base_addr = iobase; in de4x5_hw_init()
1136 printk(", h/w address %pM\n", dev->dev_addr); in de4x5_hw_init()
1140 return -ENXIO; in de4x5_hw_init()
1142 skb_queue_head_init(&lp->cache.queue); in de4x5_hw_init()
1143 lp->cache.gepc = GEP_INIT; in de4x5_hw_init()
1144 lp->asBit = GEP_SLNK; in de4x5_hw_init()
1145 lp->asPolarity = GEP_SLNK; in de4x5_hw_init()
1146 lp->asBitValid = ~0; in de4x5_hw_init()
1147 lp->timeout = -1; in de4x5_hw_init()
1148 lp->gendev = gendev; in de4x5_hw_init()
1149 spin_lock_init(&lp->lock); in de4x5_hw_init()
1150 timer_setup(&lp->timer, de4x5_ast, 0); in de4x5_hw_init()
1156 lp->autosense = lp->params.autosense; in de4x5_hw_init()
1157 if (lp->chipset != DC21140) { in de4x5_hw_init()
1158 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) { in de4x5_hw_init()
1159 lp->params.autosense = TP; in de4x5_hw_init()
1161 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) { in de4x5_hw_init()
1162 lp->params.autosense = BNC; in de4x5_hw_init()
1165 lp->fdx = lp->params.fdx; in de4x5_hw_init()
1166 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev)); in de4x5_hw_init()
1168 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc); in de4x5_hw_init()
1170 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN; in de4x5_hw_init()
1172 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size, in de4x5_hw_init()
1173 &lp->dma_rings, GFP_ATOMIC); in de4x5_hw_init()
1174 if (lp->rx_ring == NULL) { in de4x5_hw_init()
1175 return -ENOMEM; in de4x5_hw_init()
1178 lp->tx_ring = lp->rx_ring + NUM_RX_DESC; in de4x5_hw_init()
1186 lp->rx_ring[i].status = 0; in de4x5_hw_init()
1187 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); in de4x5_hw_init()
1188 lp->rx_ring[i].buf = 0; in de4x5_hw_init()
1189 lp->rx_ring[i].next = 0; in de4x5_hw_init()
1190 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */ in de4x5_hw_init()
1197 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC) in de4x5_hw_init()
1200 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC in de4x5_hw_init()
1203 lp->rx_ring[i].status = 0; in de4x5_hw_init()
1204 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); in de4x5_hw_init()
1205 lp->rx_ring[i].buf = in de4x5_hw_init()
1207 lp->rx_ring[i].next = 0; in de4x5_hw_init()
1208 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */ in de4x5_hw_init()
1216 lp->rxRingSize = NUM_RX_DESC; in de4x5_hw_init()
1217 lp->txRingSize = NUM_TX_DESC; in de4x5_hw_init()
1220 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); in de4x5_hw_init()
1221 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER); in de4x5_hw_init()
1224 outl(lp->dma_rings, DE4X5_RRBA); in de4x5_hw_init()
1225 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), in de4x5_hw_init()
1229 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM; in de4x5_hw_init()
1230 lp->irq_en = IMR_NIM | IMR_AIM; in de4x5_hw_init()
1233 create_packet(dev, lp->frame, sizeof(lp->frame)); in de4x5_hw_init()
1236 i = lp->cfrv & 0x000000fe; in de4x5_hw_init()
1237 if ((lp->chipset == DC21140) && (i == 0x20)) { in de4x5_hw_init()
1238 lp->rx_ovf = 1; in de4x5_hw_init()
1241 /* Initialise the SROM pointers if possible */ in de4x5_hw_init()
1242 if (lp->useSROM) { in de4x5_hw_init()
1243 lp->state = INITIALISED; in de4x5_hw_init()
1245 dma_free_coherent (gendev, lp->dma_size, in de4x5_hw_init()
1246 lp->rx_ring, lp->dma_rings); in de4x5_hw_init()
1247 return -ENXIO; in de4x5_hw_init()
1252 lp->state = CLOSED; in de4x5_hw_init()
1257 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) { in de4x5_hw_init()
1261 printk(" and requires IRQ%d (provided by %s).\n", dev->irq, in de4x5_hw_init()
1262 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG")); in de4x5_hw_init()
1269 /* The DE4X5-specific entries in the device structure. */ in de4x5_hw_init()
1271 dev->netdev_ops = &de4x5_netdev_ops; in de4x5_hw_init()
1272 dev->mem_start = 0; in de4x5_hw_init()
1276 dma_free_coherent (gendev, lp->dma_size, in de4x5_hw_init()
1277 lp->rx_ring, lp->dma_rings); in de4x5_hw_init()
1292 u_long iobase = dev->base_addr; in de4x5_open()
1297 for (i=0; i<lp->rxRingSize; i++) { in de4x5_open()
1300 return -EAGAIN; in de4x5_open()
1310 ** Re-initialize the DE4X5... in de4x5_open()
1313 spin_lock_init(&lp->lock); in de4x5_open()
1314 lp->state = OPEN; in de4x5_open()
1317 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED, in de4x5_open()
1318 lp->adapter_name, dev)) { in de4x5_open()
1319 printk("de4x5_open(): Requested IRQ%d is busy - attempting FAST/SHARE...", dev->irq); in de4x5_open()
1320 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED, in de4x5_open()
1321 lp->adapter_name, dev)) { in de4x5_open()
1322 printk("\n Cannot get IRQ- reconfigure your hardware.\n"); in de4x5_open()
1327 lp->state = CLOSED; in de4x5_open()
1328 return -EAGAIN; in de4x5_open()
1335 lp->interrupt = UNMASK_INTERRUPTS; in de4x5_open()
1358 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1360 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1382 u_long iobase = dev->base_addr; in de4x5_sw_reset()
1387 if (!lp->useSROM) { in de4x5_sw_reset()
1388 if (lp->phy[lp->active].id != 0) { in de4x5_sw_reset()
1389 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD; in de4x5_sw_reset()
1391 lp->infoblock_csr6 = OMR_SDP | OMR_TTM; in de4x5_sw_reset()
1401 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN; in de4x5_sw_reset()
1402 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0); in de4x5_sw_reset()
1405 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */ in de4x5_sw_reset()
1406 if (lp->chipset == DC21140) { in de4x5_sw_reset()
1409 lp->setup_f = PERFECT; in de4x5_sw_reset()
1410 outl(lp->dma_rings, DE4X5_RRBA); in de4x5_sw_reset()
1411 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), in de4x5_sw_reset()
1414 lp->rx_new = lp->rx_old = 0; in de4x5_sw_reset()
1415 lp->tx_new = lp->tx_old = 0; in de4x5_sw_reset()
1417 for (i = 0; i < lp->rxRingSize; i++) { in de4x5_sw_reset()
1418 lp->rx_ring[i].status = cpu_to_le32(R_OWN); in de4x5_sw_reset()
1421 for (i = 0; i < lp->txRingSize; i++) { in de4x5_sw_reset()
1422 lp->tx_ring[i].status = cpu_to_le32(0); in de4x5_sw_reset()
1427 /* Build the setup frame depending on filtering mode */ in de4x5_sw_reset()
1430 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1); in de4x5_sw_reset()
1437 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1; in de4x5_sw_reset()
1442 printk("%s: Setup frame timed out, status %08x\n", dev->name, in de4x5_sw_reset()
1444 status = -EIO; in de4x5_sw_reset()
1447 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize; in de4x5_sw_reset()
1448 lp->tx_old = lp->tx_new; in de4x5_sw_reset()
1460 u_long iobase = dev->base_addr; in de4x5_queue_pkt()
1464 if (!lp->tx_enable) /* Cannot send for now */ in de4x5_queue_pkt()
1468 ** Clean out the TX ring asynchronously to interrupts - sometimes the in de4x5_queue_pkt()
1472 spin_lock_irqsave(&lp->lock, flags); in de4x5_queue_pkt()
1474 spin_unlock_irqrestore(&lp->lock, flags); in de4x5_queue_pkt()
1476 /* Test if cache is already locked - requeue skb if so */ in de4x5_queue_pkt()
1477 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt) in de4x5_queue_pkt()
1481 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) { in de4x5_queue_pkt()
1482 if (lp->interrupt) { in de4x5_queue_pkt()
1488 …\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5… in de4x5_queue_pkt()
1490 } else if (skb->len > 0) { in de4x5_queue_pkt()
1492 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) { in de4x5_queue_pkt()
1498 (u_long) lp->tx_skb[lp->tx_new] <= 1) { in de4x5_queue_pkt()
1499 spin_lock_irqsave(&lp->lock, flags); in de4x5_queue_pkt()
1501 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb); in de4x5_queue_pkt()
1502 lp->stats.tx_bytes += skb->len; in de4x5_queue_pkt()
1505 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize; in de4x5_queue_pkt()
1511 spin_unlock_irqrestore(&lp->lock, flags); in de4x5_queue_pkt()
1516 lp->cache.lock = 0; in de4x5_queue_pkt()
1528 ** so that the asserted interrupt always has some real data to work with -
1545 spin_lock(&lp->lock); in de4x5_interrupt()
1546 iobase = dev->base_addr; in de4x5_interrupt()
1548 DISABLE_IRQs; /* Ensure non re-entrancy */ in de4x5_interrupt()
1550 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt)) in de4x5_interrupt()
1551 printk("%s: Re-entering the interrupt handler.\n", dev->name); in de4x5_interrupt()
1553 synchronize_irq(dev->irq); in de4x5_interrupt()
1559 if (!(sts & lp->irq_mask)) break;/* All done */ in de4x5_interrupt()
1569 lp->irq_mask &= ~IMR_LFM; in de4x5_interrupt()
1579 dev->name, sts); in de4x5_interrupt()
1580 spin_unlock(&lp->lock); in de4x5_interrupt()
1586 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) { in de4x5_interrupt()
1587 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) { in de4x5_interrupt()
1590 lp->cache.lock = 0; in de4x5_interrupt()
1593 lp->interrupt = UNMASK_INTERRUPTS; in de4x5_interrupt()
1595 spin_unlock(&lp->lock); in de4x5_interrupt()
1604 u_long iobase = dev->base_addr; in de4x5_rx()
1608 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0; in de4x5_rx()
1609 entry=lp->rx_new) { in de4x5_rx()
1610 status = (s32)le32_to_cpu(lp->rx_ring[entry].status); in de4x5_rx()
1612 if (lp->rx_ovf) { in de4x5_rx()
1620 lp->rx_old = entry; in de4x5_rx()
1624 if (lp->tx_enable) lp->linkOK++; in de4x5_rx()
1626 lp->stats.rx_errors++; /* Update the error stats. */ in de4x5_rx()
1627 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++; in de4x5_rx()
1628 if (status & RD_CE) lp->stats.rx_crc_errors++; in de4x5_rx()
1629 if (status & RD_OF) lp->stats.rx_fifo_errors++; in de4x5_rx()
1630 if (status & RD_TL) lp->stats.rx_length_errors++; in de4x5_rx()
1631 if (status & RD_RF) lp->pktStats.rx_runt_frames++; in de4x5_rx()
1632 if (status & RD_CS) lp->pktStats.rx_collision++; in de4x5_rx()
1633 if (status & RD_DB) lp->pktStats.rx_dribble++; in de4x5_rx()
1634 if (status & RD_OF) lp->pktStats.rx_overflow++; in de4x5_rx()
1637 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status) in de4x5_rx()
1638 >> 16) - 4; in de4x5_rx()
1642 dev->name); in de4x5_rx()
1643 lp->stats.rx_dropped++; in de4x5_rx()
1648 skb->protocol=eth_type_trans(skb,dev); in de4x5_rx()
1649 de4x5_local_stats(dev, skb->data, pkt_len); in de4x5_rx()
1653 lp->stats.rx_packets++; in de4x5_rx()
1654 lp->stats.rx_bytes += pkt_len; in de4x5_rx()
1659 for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) { in de4x5_rx()
1660 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN); in de4x5_rx()
1663 lp->rx_ring[entry].status = cpu_to_le32(R_OWN); in de4x5_rx()
1670 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize; in de4x5_rx()
1679 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf), in de4x5_free_tx_buff()
1680 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1, in de4x5_free_tx_buff()
1682 if ((u_long) lp->tx_skb[entry] > 1) in de4x5_free_tx_buff()
1683 dev_kfree_skb_irq(lp->tx_skb[entry]); in de4x5_free_tx_buff()
1684 lp->tx_skb[entry] = NULL; in de4x5_free_tx_buff()
1688 ** Buffer sent - check for TX buffer errors.
1694 u_long iobase = dev->base_addr; in de4x5_tx()
1698 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) { in de4x5_tx()
1699 status = (s32)le32_to_cpu(lp->tx_ring[entry].status); in de4x5_tx()
1704 lp->stats.tx_errors++; in de4x5_tx()
1705 if (status & TD_NC) lp->stats.tx_carrier_errors++; in de4x5_tx()
1706 if (status & TD_LC) lp->stats.tx_window_errors++; in de4x5_tx()
1707 if (status & TD_UF) lp->stats.tx_fifo_errors++; in de4x5_tx()
1708 if (status & TD_EC) lp->pktStats.excessive_collisions++; in de4x5_tx()
1709 if (status & TD_DE) lp->stats.tx_aborted_errors++; in de4x5_tx()
1715 lp->stats.tx_packets++; in de4x5_tx()
1716 if (lp->tx_enable) lp->linkOK++; in de4x5_tx()
1719 lp->stats.collisions += ((status & TD_EC) ? 16 : in de4x5_tx()
1723 if (lp->tx_skb[entry] != NULL) in de4x5_tx()
1728 lp->tx_old = (lp->tx_old + 1) % lp->txRingSize; in de4x5_tx()
1733 if (lp->interrupt) in de4x5_tx()
1746 struct net_device *dev = dev_get_drvdata(lp->gendev); in de4x5_ast()
1750 if (lp->useSROM) in de4x5_ast()
1752 else if (lp->chipset == DC21140) in de4x5_ast()
1754 else if (lp->chipset == DC21041) in de4x5_ast()
1756 else if (lp->chipset == DC21040) in de4x5_ast()
1758 lp->linkOK = 0; in de4x5_ast()
1765 mod_timer(&lp->timer, jiffies + dt); in de4x5_ast()
1772 u_long iobase = dev->base_addr; in de4x5_txur()
1776 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) { in de4x5_txur()
1795 u_long iobase = dev->base_addr; in de4x5_rx_ovfc()
1802 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) { in de4x5_rx_ovfc()
1803 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN); in de4x5_rx_ovfc()
1804 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize; in de4x5_rx_ovfc()
1816 u_long iobase = dev->base_addr; in de4x5_close()
1825 dev->name, inl(DE4X5_STS)); in de4x5_close()
1835 free_irq(dev->irq, dev); in de4x5_close()
1836 lp->state = CLOSED; in de4x5_close()
1852 u_long iobase = dev->base_addr; in de4x5_get_stats()
1854 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR)); in de4x5_get_stats()
1856 return &lp->stats; in de4x5_get_stats()
1865 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) { in de4x5_local_stats()
1867 lp->pktStats.bins[i]++; in de4x5_local_stats()
1873 lp->pktStats.broadcast++; in de4x5_local_stats()
1875 lp->pktStats.multicast++; in de4x5_local_stats()
1877 } else if (ether_addr_equal(buf, dev->dev_addr)) { in de4x5_local_stats()
1878 lp->pktStats.unicast++; in de4x5_local_stats()
1881 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */ in de4x5_local_stats()
1882 if (lp->pktStats.bins[0] == 0) { /* Reset counters */ in de4x5_local_stats()
1883 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats)); in de4x5_local_stats()
1899 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1); in load_packet()
1900 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE); in load_packet()
1902 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma); in load_packet()
1903 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER); in load_packet()
1904 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags); in load_packet()
1905 lp->tx_skb[lp->tx_new] = skb; in load_packet()
1906 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC); in load_packet()
1909 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN); in load_packet()
1920 u_long iobase = dev->base_addr; in set_multicast_list()
1923 if (lp->state == OPEN) { in set_multicast_list()
1924 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ in set_multicast_list()
1931 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET | in set_multicast_list()
1934 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize; in set_multicast_list()
1951 u_long iobase = dev->base_addr; in SetMulticastFilter()
1962 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 14)) { in SetMulticastFilter()
1964 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */ in SetMulticastFilter()
1966 crc = ether_crc_le(ETH_ALEN, ha->addr); in SetMulticastFilter()
1969 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */ in SetMulticastFilter()
1970 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */ in SetMulticastFilter()
1974 byte -= 1; in SetMulticastFilter()
1976 lp->setup_frame[byte] |= bit; in SetMulticastFilter()
1980 addrs = ha->addr; in SetMulticastFilter()
2006 iobase = edev->base_addr; in de4x5_eisa_probe()
2009 return -EBUSY; in de4x5_eisa_probe()
2013 status = -EBUSY; in de4x5_eisa_probe()
2018 status = -ENOMEM; in de4x5_eisa_probe()
2024 lp->cfrv = (u_short) inl(PCI_CFRV); in de4x5_eisa_probe()
2053 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); in de4x5_eisa_probe()
2055 lp->chipset = device; in de4x5_eisa_probe()
2056 lp->bus = EISA; in de4x5_eisa_probe()
2065 dev->irq = irq; in de4x5_eisa_probe()
2086 iobase = dev->base_addr; in de4x5_eisa_remove()
2116 ** SROM, so that in multiport cards that have one SROM shared between multiple
2117 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2131 list_for_each_entry(this_dev, &pdev->bus->devices, bus_list) { in srom_search()
2132 vendor = this_dev->vendor; in srom_search()
2133 device = this_dev->device << 8; in srom_search()
2137 pb = this_dev->bus->number; in srom_search()
2140 lp->device = PCI_SLOT(this_dev->devfn); in srom_search()
2141 lp->bus_num = pb; in srom_search()
2145 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK in srom_search()
2148 lp->chipset = device; in srom_search()
2154 irq = this_dev->irq; in srom_search()
2155 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue; in srom_search()
2161 /* Search for a valid SROM attached to this DECchip */ in srom_search()
2164 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i); in srom_search()
2171 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i); in srom_search()
2205 dev_num = PCI_SLOT(pdev->devfn); in de4x5_pci_probe()
2206 pb = pdev->bus->number; in de4x5_pci_probe()
2212 return -ENODEV; in de4x5_pci_probe()
2215 vendor = pdev->vendor; in de4x5_pci_probe()
2216 device = pdev->device << 8; in de4x5_pci_probe()
2218 return -ENODEV; in de4x5_pci_probe()
2225 error = -ENOMEM; in de4x5_pci_probe()
2230 lp->bus = PCI; in de4x5_pci_probe()
2231 lp->bus_num = 0; in de4x5_pci_probe()
2233 /* Search for an SROM on this bus */ in de4x5_pci_probe()
2234 if (lp->bus_num != pb) { in de4x5_pci_probe()
2235 lp->bus_num = pb; in de4x5_pci_probe()
2240 lp->cfrv = pdev->revision; in de4x5_pci_probe()
2243 lp->device = dev_num; in de4x5_pci_probe()
2244 lp->bus_num = pb; in de4x5_pci_probe()
2248 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); in de4x5_pci_probe()
2250 lp->chipset = device; in de4x5_pci_probe()
2256 irq = pdev->irq; in de4x5_pci_probe()
2257 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) { in de4x5_pci_probe()
2258 error = -ENODEV; in de4x5_pci_probe()
2272 error = -ENODEV; in de4x5_pci_probe()
2282 error = -ENODEV; in de4x5_pci_probe()
2295 error = -EBUSY; in de4x5_pci_probe()
2299 dev->irq = irq; in de4x5_pci_probe()
2301 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) { in de4x5_pci_probe()
2322 iobase = dev->base_addr; in de4x5_pci_remove()
2362 u_long iobase = dev->base_addr; in autoconf_media()
2366 lp->c_media = AUTO; /* Bogus last media */ in autoconf_media()
2368 lp->media = INIT; in autoconf_media()
2369 lp->tcount = 0; in autoconf_media()
2371 de4x5_ast(&lp->timer); in autoconf_media()
2373 return lp->media; in autoconf_media()
2383 ** be queued to the hardware. Re-enable everything only when the media is
2392 u_long iobase = dev->base_addr; in dc21040_autoconf()
2396 switch (lp->media) { in dc21040_autoconf()
2399 lp->tx_enable = false; in dc21040_autoconf()
2400 lp->timeout = -1; in dc21040_autoconf()
2402 if ((lp->autosense == AUTO) || (lp->autosense == TP)) { in dc21040_autoconf()
2403 lp->media = TP; in dc21040_autoconf()
2404 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) { in dc21040_autoconf()
2405 lp->media = BNC_AUI; in dc21040_autoconf()
2406 } else if (lp->autosense == EXT_SIA) { in dc21040_autoconf()
2407 lp->media = EXT_SIA; in dc21040_autoconf()
2409 lp->media = NC; in dc21040_autoconf()
2411 lp->local_state = 0; in dc21040_autoconf()
2447 if (lp->media != lp->c_media) { in dc21040_autoconf()
2449 lp->c_media = lp->media; in dc21040_autoconf()
2451 lp->media = INIT; in dc21040_autoconf()
2452 lp->tx_enable = false; in dc21040_autoconf()
2468 switch (lp->local_state) { in dc21040_state()
2471 lp->local_state++; in dc21040_state()
2476 if (!lp->tx_enable) { in dc21040_state()
2481 if (linkBad && (lp->autosense == AUTO)) { in dc21040_state()
2482 lp->local_state = 0; in dc21040_state()
2483 lp->media = next_state; in dc21040_state()
2488 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21040_state()
2489 lp->media = suspect_state; in dc21040_state()
2507 switch (lp->local_state) { in de4x5_suspect_state()
2509 if (lp->linkOK) { in de4x5_suspect_state()
2510 lp->media = prev_state; in de4x5_suspect_state()
2512 lp->local_state++; in de4x5_suspect_state()
2522 lp->local_state--; in de4x5_suspect_state()
2523 lp->media = prev_state; in de4x5_suspect_state()
2525 lp->media = INIT; in de4x5_suspect_state()
2526 lp->tcount++; in de4x5_suspect_state()
2539 ** any more packets to be queued to the hardware. Re-enable everything only
2546 u_long iobase = dev->base_addr; in dc21041_autoconf()
2550 switch (lp->media) { in dc21041_autoconf()
2553 lp->tx_enable = false; in dc21041_autoconf()
2554 lp->timeout = -1; in dc21041_autoconf()
2556 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) { in dc21041_autoconf()
2557 lp->media = TP; /* On chip auto negotiation is broken */ in dc21041_autoconf()
2558 } else if (lp->autosense == TP) { in dc21041_autoconf()
2559 lp->media = TP; in dc21041_autoconf()
2560 } else if (lp->autosense == BNC) { in dc21041_autoconf()
2561 lp->media = BNC; in dc21041_autoconf()
2562 } else if (lp->autosense == AUI) { in dc21041_autoconf()
2563 lp->media = AUI; in dc21041_autoconf()
2565 lp->media = NC; in dc21041_autoconf()
2567 lp->local_state = 0; in dc21041_autoconf()
2572 if (lp->timeout < 0) { in dc21041_autoconf()
2583 lp->media = ANS; in dc21041_autoconf()
2585 lp->media = AUI; in dc21041_autoconf()
2592 if (!lp->tx_enable) { in dc21041_autoconf()
2599 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) { in dc21041_autoconf()
2600 lp->media = TP; in dc21041_autoconf()
2603 lp->local_state = 1; in dc21041_autoconf()
2607 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21041_autoconf()
2608 lp->media = ANS_SUSPECT; in dc21041_autoconf()
2618 if (!lp->tx_enable) { in dc21041_autoconf()
2619 if (lp->timeout < 0) { in dc21041_autoconf()
2629 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) { in dc21041_autoconf()
2631 lp->media = AUI; /* Non selected port activity */ in dc21041_autoconf()
2633 lp->media = BNC; in dc21041_autoconf()
2637 lp->local_state = 1; in dc21041_autoconf()
2641 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21041_autoconf()
2642 lp->media = TP_SUSPECT; in dc21041_autoconf()
2652 if (!lp->tx_enable) { in dc21041_autoconf()
2653 if (lp->timeout < 0) { in dc21041_autoconf()
2663 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) { in dc21041_autoconf()
2664 lp->media = BNC; in dc21041_autoconf()
2667 lp->local_state = 1; in dc21041_autoconf()
2671 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21041_autoconf()
2672 lp->media = AUI_SUSPECT; in dc21041_autoconf()
2682 switch (lp->local_state) { in dc21041_autoconf()
2684 if (lp->timeout < 0) { in dc21041_autoconf()
2694 lp->local_state++; /* Ensure media connected */ in dc21041_autoconf()
2700 if (!lp->tx_enable) { in dc21041_autoconf()
2705 lp->local_state = 0; in dc21041_autoconf()
2706 lp->media = NC; in dc21041_autoconf()
2711 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21041_autoconf()
2712 lp->media = BNC_SUSPECT; in dc21041_autoconf()
2727 if (lp->media != lp->c_media) { in dc21041_autoconf()
2729 lp->c_media = lp->media; in dc21041_autoconf()
2731 lp->media = INIT; in dc21041_autoconf()
2732 lp->tx_enable = false; in dc21041_autoconf()
2750 u_long imr, omr, iobase = dev->base_addr; in dc21140m_autoconf()
2752 switch(lp->media) { in dc21140m_autoconf()
2754 if (lp->timeout < 0) { in dc21140m_autoconf()
2756 lp->tx_enable = false; in dc21140m_autoconf()
2757 lp->linkOK = 0; in dc21140m_autoconf()
2763 if (lp->useSROM) { in dc21140m_autoconf()
2765 lp->tcount++; in dc21140m_autoconf()
2768 srom_exec(dev, lp->phy[lp->active].gep); in dc21140m_autoconf()
2769 if (lp->infoblock_media == ANS) { in dc21140m_autoconf()
2770 ana = lp->phy[lp->active].ana | MII_ANA_CSMA; in dc21140m_autoconf()
2771 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); in dc21140m_autoconf()
2774 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */ in dc21140m_autoconf()
2776 if (lp->autosense == _100Mb) { in dc21140m_autoconf()
2777 lp->media = _100Mb; in dc21140m_autoconf()
2778 } else if (lp->autosense == _10Mb) { in dc21140m_autoconf()
2779 lp->media = _10Mb; in dc21140m_autoconf()
2780 } else if ((lp->autosense == AUTO) && in dc21140m_autoconf()
2783 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM); in dc21140m_autoconf()
2784 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); in dc21140m_autoconf()
2785 lp->media = ANS; in dc21140m_autoconf()
2786 } else if (lp->autosense == AUTO) { in dc21140m_autoconf()
2787 lp->media = SPD_DET; in dc21140m_autoconf()
2789 lp->media = _100Mb; in dc21140m_autoconf()
2791 lp->media = NC; in dc21140m_autoconf()
2794 lp->local_state = 0; in dc21140m_autoconf()
2800 switch (lp->local_state) { in dc21140m_autoconf()
2802 if (lp->timeout < 0) { in dc21140m_autoconf()
2803 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); in dc21140m_autoconf()
2810 lp->local_state = 0; in dc21140m_autoconf()
2811 lp->media = SPD_DET; in dc21140m_autoconf()
2813 lp->local_state++; in dc21140m_autoconf()
2823 lp->media = SPD_DET; in dc21140m_autoconf()
2824 lp->local_state = 0; in dc21140m_autoconf()
2826 lp->tmp = MII_SR_ASSC; in dc21140m_autoconf()
2827 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII); in dc21140m_autoconf()
2828 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); in dc21140m_autoconf()
2832 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0; in dc21140m_autoconf()
2833 lp->media = _100Mb; in dc21140m_autoconf()
2835 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0; in dc21140m_autoconf()
2837 lp->media = _10Mb; in dc21140m_autoconf()
2848 if (lp->timeout < 0) { in dc21140m_autoconf()
2849 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS : in dc21140m_autoconf()
2857 lp->media = _100Mb; in dc21140m_autoconf()
2858 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) { in dc21140m_autoconf()
2859 lp->media = _10Mb; in dc21140m_autoconf()
2861 lp->media = NC; in dc21140m_autoconf()
2869 if (!lp->tx_enable) { in dc21140m_autoconf()
2873 if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21140m_autoconf()
2874 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) { in dc21140m_autoconf()
2875 lp->media = INIT; in dc21140m_autoconf()
2876 lp->tcount++; in dc21140m_autoconf()
2887 if (!lp->tx_enable) { in dc21140m_autoconf()
2891 if (!lp->linkOK && (lp->autosense == AUTO)) { in dc21140m_autoconf()
2892 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) { in dc21140m_autoconf()
2893 lp->media = INIT; in dc21140m_autoconf()
2894 lp->tcount++; in dc21140m_autoconf()
2902 if (lp->media != lp->c_media) { in dc21140m_autoconf()
2904 lp->c_media = lp->media; in dc21140m_autoconf()
2906 lp->media = INIT; in dc21140m_autoconf()
2907 lp->tx_enable = false; in dc21140m_autoconf()
2916 ** changing how I figure out the media - but trying to keep it backwards
2917 ** compatible with the de500-xa and de500-aa.
2922 ** When autonegotiation is working, the ANS part searches the SROM for
2932 u_long iobase = dev->base_addr; in dc2114x_autoconf()
2936 switch (lp->media) { in dc2114x_autoconf()
2938 if (lp->timeout < 0) { in dc2114x_autoconf()
2940 lp->tx_enable = false; in dc2114x_autoconf()
2941 lp->linkOK = 0; in dc2114x_autoconf()
2942 lp->timeout = -1; in dc2114x_autoconf()
2944 if (lp->params.autosense & ~AUTO) { in dc2114x_autoconf()
2946 if (lp->media != lp->params.autosense) { in dc2114x_autoconf()
2947 lp->tcount++; in dc2114x_autoconf()
2948 lp->media = INIT; in dc2114x_autoconf()
2951 lp->media = INIT; in dc2114x_autoconf()
2957 if (lp->autosense == _100Mb) { in dc2114x_autoconf()
2958 lp->media = _100Mb; in dc2114x_autoconf()
2959 } else if (lp->autosense == _10Mb) { in dc2114x_autoconf()
2960 lp->media = _10Mb; in dc2114x_autoconf()
2961 } else if (lp->autosense == TP) { in dc2114x_autoconf()
2962 lp->media = TP; in dc2114x_autoconf()
2963 } else if (lp->autosense == BNC) { in dc2114x_autoconf()
2964 lp->media = BNC; in dc2114x_autoconf()
2965 } else if (lp->autosense == AUI) { in dc2114x_autoconf()
2966 lp->media = AUI; in dc2114x_autoconf()
2968 lp->media = SPD_DET; in dc2114x_autoconf()
2969 if ((lp->infoblock_media == ANS) && in dc2114x_autoconf()
2972 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM); in dc2114x_autoconf()
2973 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); in dc2114x_autoconf()
2974 lp->media = ANS; in dc2114x_autoconf()
2977 lp->local_state = 0; in dc2114x_autoconf()
2983 switch (lp->local_state) { in dc2114x_autoconf()
2985 if (lp->timeout < 0) { in dc2114x_autoconf()
2986 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); in dc2114x_autoconf()
2993 lp->local_state = 0; in dc2114x_autoconf()
2994 lp->media = SPD_DET; in dc2114x_autoconf()
2996 lp->local_state++; in dc2114x_autoconf()
3007 lp->media = SPD_DET; in dc2114x_autoconf()
3008 lp->local_state = 0; in dc2114x_autoconf()
3010 lp->tmp = MII_SR_ASSC; in dc2114x_autoconf()
3011 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII); in dc2114x_autoconf()
3012 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); in dc2114x_autoconf()
3016 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0; in dc2114x_autoconf()
3017 lp->media = _100Mb; in dc2114x_autoconf()
3019 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0; in dc2114x_autoconf()
3020 lp->media = _10Mb; in dc2114x_autoconf()
3031 if (!lp->tx_enable) { in dc2114x_autoconf()
3032 if (lp->timeout < 0) { in dc2114x_autoconf()
3042 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) { in dc2114x_autoconf()
3043 lp->media = BNC; in dc2114x_autoconf()
3046 lp->local_state = 1; in dc2114x_autoconf()
3050 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc2114x_autoconf()
3051 lp->media = AUI_SUSPECT; in dc2114x_autoconf()
3061 switch (lp->local_state) { in dc2114x_autoconf()
3063 if (lp->timeout < 0) { in dc2114x_autoconf()
3073 lp->local_state++; /* Ensure media connected */ in dc2114x_autoconf()
3079 if (!lp->tx_enable) { in dc2114x_autoconf()
3084 lp->local_state = 0; in dc2114x_autoconf()
3085 lp->tcount++; in dc2114x_autoconf()
3086 lp->media = INIT; in dc2114x_autoconf()
3091 } else if (!lp->linkOK && (lp->autosense == AUTO)) { in dc2114x_autoconf()
3092 lp->media = BNC_SUSPECT; in dc2114x_autoconf()
3105 lp->tcount++; in dc2114x_autoconf()
3106 lp->media = INIT; in dc2114x_autoconf()
3109 if (lp->media == _100Mb) { in dc2114x_autoconf()
3111 lp->media = SPD_DET; in dc2114x_autoconf()
3116 lp->media = SPD_DET; in dc2114x_autoconf()
3120 if (lp->media == ANS) { /* Do MII parallel detection */ in dc2114x_autoconf()
3122 lp->media = _100Mb; in dc2114x_autoconf()
3124 lp->media = _10Mb; in dc2114x_autoconf()
3127 } else if (((lp->media == _100Mb) && is_100_up(dev)) || in dc2114x_autoconf()
3128 (((lp->media == _10Mb) || (lp->media == TP) || in dc2114x_autoconf()
3129 (lp->media == BNC) || (lp->media == AUI)) && in dc2114x_autoconf()
3133 lp->tcount++; in dc2114x_autoconf()
3134 lp->media = INIT; in dc2114x_autoconf()
3140 if (!lp->tx_enable) { in dc2114x_autoconf()
3144 if (!lp->linkOK && (lp->autosense == AUTO)) { in dc2114x_autoconf()
3145 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) { in dc2114x_autoconf()
3146 lp->media = INIT; in dc2114x_autoconf()
3147 lp->tcount++; in dc2114x_autoconf()
3156 if (!lp->tx_enable) { in dc2114x_autoconf()
3160 if (!lp->linkOK && (lp->autosense == AUTO)) { in dc2114x_autoconf()
3161 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) { in dc2114x_autoconf()
3162 lp->media = INIT; in dc2114x_autoconf()
3163 lp->tcount++; in dc2114x_autoconf()
3171 lp->tcount++; in dc2114x_autoconf()
3172 printk("Huh?: media:%02x\n", lp->media); in dc2114x_autoconf()
3173 lp->media = INIT; in dc2114x_autoconf()
3185 return lp->infoleaf_fn(dev); in srom_autoconf()
3191 ** The early return avoids a media state / SROM media space clash.
3198 lp->fdx = false; in srom_map_media()
3199 if (lp->infoblock_media == lp->media) in srom_map_media()
3202 switch(lp->infoblock_media) { in srom_map_media()
3204 if (!lp->params.fdx) return -1; in srom_map_media()
3205 lp->fdx = true; in srom_map_media()
3209 if (lp->params.fdx && !lp->fdx) return -1; in srom_map_media()
3210 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) { in srom_map_media()
3211 lp->media = _10Mb; in srom_map_media()
3213 lp->media = TP; in srom_map_media()
3218 lp->media = BNC; in srom_map_media()
3222 lp->media = AUI; in srom_map_media()
3226 if (!lp->params.fdx) return -1; in srom_map_media()
3227 lp->fdx = true; in srom_map_media()
3231 if (lp->params.fdx && !lp->fdx) return -1; in srom_map_media()
3232 lp->media = _100Mb; in srom_map_media()
3236 lp->media = _100Mb; in srom_map_media()
3240 if (!lp->params.fdx) return -1; in srom_map_media()
3241 lp->fdx = true; in srom_map_media()
3245 if (lp->params.fdx && !lp->fdx) return -1; in srom_map_media()
3246 lp->media = _100Mb; in srom_map_media()
3250 lp->media = ANS; in srom_map_media()
3251 lp->fdx = lp->params.fdx; in srom_map_media()
3255 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name, in srom_map_media()
3256 lp->infoblock_media); in srom_map_media()
3257 return -1; in srom_map_media()
3267 u_long iobase = dev->base_addr; in de4x5_init_connection()
3270 if (lp->media != lp->c_media) { in de4x5_init_connection()
3272 lp->c_media = lp->media; /* Stop scrolling media messages */ in de4x5_init_connection()
3275 spin_lock_irqsave(&lp->lock, flags); in de4x5_init_connection()
3278 lp->tx_enable = true; in de4x5_init_connection()
3279 spin_unlock_irqrestore(&lp->lock, flags); in de4x5_init_connection()
3294 u_long iobase = dev->base_addr; in de4x5_reset_phy()
3297 if ((lp->useSROM) || (lp->phy[lp->active].id)) { in de4x5_reset_phy()
3298 if (lp->timeout < 0) { in de4x5_reset_phy()
3299 if (lp->useSROM) { in de4x5_reset_phy()
3300 if (lp->phy[lp->active].rst) { in de4x5_reset_phy()
3301 srom_exec(dev, lp->phy[lp->active].rst); in de4x5_reset_phy()
3302 srom_exec(dev, lp->phy[lp->active].rst); in de4x5_reset_phy()
3303 } else if (lp->rst) { /* Type 5 infoblock reset */ in de4x5_reset_phy()
3304 srom_exec(dev, lp->rst); in de4x5_reset_phy()
3305 srom_exec(dev, lp->rst); in de4x5_reset_phy()
3310 if (lp->useMII) { in de4x5_reset_phy()
3311 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); in de4x5_reset_phy()
3314 if (lp->useMII) { in de4x5_reset_phy()
3317 } else if (lp->chipset == DC21140) { in de4x5_reset_phy()
3328 u_long iobase = dev->base_addr; in test_media()
3331 if (lp->timeout < 0) { in test_media()
3332 lp->timeout = msec/100; in test_media()
3333 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */ in test_media()
3345 if ((lp->chipset == DC21041) || lp->useSROM) { in test_media()
3353 if (!(sts & irqs) && --lp->timeout) { in test_media()
3356 lp->timeout = -1; in test_media()
3366 u_long iobase = dev->base_addr; in test_tp()
3369 if (lp->timeout < 0) { in test_tp()
3370 lp->timeout = msec/100; in test_tp()
3375 if (sisr && --lp->timeout) { in test_tp()
3378 lp->timeout = -1; in test_tp()
3395 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK); in test_for_100Mb()
3397 if (lp->timeout < 0) { in test_for_100Mb()
3400 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL; in test_for_100Mb()
3404 lp->timeout = msec/SAMPLE_INTERVAL; in test_for_100Mb()
3408 if (lp->phy[lp->active].id || lp->useSROM) { in test_for_100Mb()
3413 if (!(gep & ret) && --lp->timeout) { in test_for_100Mb()
3416 lp->timeout = -1; in test_for_100Mb()
3427 if (lp->timeout < 0) { in wait_for_link()
3428 lp->timeout = 1; in wait_for_link()
3431 if (lp->timeout--) { in wait_for_link()
3434 lp->timeout = -1; in wait_for_link()
3449 u_long iobase = dev->base_addr; in test_mii_reg()
3451 if (lp->timeout < 0) { in test_mii_reg()
3452 lp->timeout = msec/100; in test_mii_reg()
3455 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask; in test_mii_reg()
3458 if (test && --lp->timeout) { in test_mii_reg()
3461 lp->timeout = -1; in test_mii_reg()
3471 u_long iobase = dev->base_addr; in is_spd_100()
3474 if (lp->useMII) { in is_spd_100()
3475 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII); in is_spd_100()
3476 spd = ~(spd ^ lp->phy[lp->active].spd.value); in is_spd_100()
3477 spd &= lp->phy[lp->active].spd.mask; in is_spd_100()
3478 } else if (!lp->useSROM) { /* de500-xa */ in is_spd_100()
3481 if ((lp->ibn == 2) || !lp->asBitValid) in is_spd_100()
3482 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0; in is_spd_100()
3484 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) | in is_spd_100()
3485 (lp->linkOK & ~lp->asBitValid); in is_spd_100()
3495 u_long iobase = dev->base_addr; in is_100_up()
3497 if (lp->useMII) { in is_100_up()
3499 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); in is_100_up()
3500 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS; in is_100_up()
3501 } else if (!lp->useSROM) { /* de500-xa */ in is_100_up()
3504 if ((lp->ibn == 2) || !lp->asBitValid) in is_100_up()
3505 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0; in is_100_up()
3507 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) | in is_100_up()
3508 (lp->linkOK & ~lp->asBitValid); in is_100_up()
3516 u_long iobase = dev->base_addr; in is_10_up()
3518 if (lp->useMII) { in is_10_up()
3520 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); in is_10_up()
3521 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS; in is_10_up()
3522 } else if (!lp->useSROM) { /* de500-xa */ in is_10_up()
3525 if ((lp->ibn == 2) || !lp->asBitValid) in is_10_up()
3526 return ((lp->chipset & ~0x00ff) == DC2114x) ? in is_10_up()
3530 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) | in is_10_up()
3531 (lp->linkOK & ~lp->asBitValid); in is_10_up()
3539 u_long iobase = dev->base_addr; in is_anc_capable()
3541 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) { in is_anc_capable()
3542 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); in is_anc_capable()
3543 } else if ((lp->chipset & ~0x00ff) == DC2114x) { in is_anc_capable()
3558 u_long iobase = dev->base_addr; in ping_media()
3561 if (lp->timeout < 0) { in ping_media()
3562 lp->timeout = msec/100; in ping_media()
3564 lp->tmp = lp->tx_new; /* Remember the ring position */ in ping_media()
3565 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1); in ping_media()
3566 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize; in ping_media()
3573 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) && in ping_media()
3574 (--lp->timeout)) { in ping_media()
3578 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) && in ping_media()
3579 lp->timeout) { in ping_media()
3584 lp->timeout = -1; in ping_media()
3608 tmp = virt_to_bus(p->data); in de4x5_alloc_rx_buff()
3609 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp; in de4x5_alloc_rx_buff()
3611 lp->rx_ring[index].buf = cpu_to_le32(tmp + i); in de4x5_alloc_rx_buff()
3613 ret = lp->rx_skb[index]; in de4x5_alloc_rx_buff()
3614 lp->rx_skb[index] = p; in de4x5_alloc_rx_buff()
3623 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */ in de4x5_alloc_rx_buff()
3629 if (index < lp->rx_old) { /* Wrapped buffer */ in de4x5_alloc_rx_buff()
3630 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ; in de4x5_alloc_rx_buff()
3631 skb_put_data(p, lp->rx_bufs + lp->rx_old * RX_BUFF_SZ, tlen); in de4x5_alloc_rx_buff()
3632 skb_put_data(p, lp->rx_bufs, len - tlen); in de4x5_alloc_rx_buff()
3634 skb_put_data(p, lp->rx_bufs + lp->rx_old * RX_BUFF_SZ, len); in de4x5_alloc_rx_buff()
3647 for (i=0; i<lp->rxRingSize; i++) { in de4x5_free_rx_buffs()
3648 if ((u_long) lp->rx_skb[i] > 1) { in de4x5_free_rx_buffs()
3649 dev_kfree_skb(lp->rx_skb[i]); in de4x5_free_rx_buffs()
3651 lp->rx_ring[i].status = 0; in de4x5_free_rx_buffs()
3652 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */ in de4x5_free_rx_buffs()
3662 for (i=0; i<lp->txRingSize; i++) { in de4x5_free_tx_buffs()
3663 if (lp->tx_skb[i]) in de4x5_free_tx_buffs()
3665 lp->tx_ring[i].status = 0; in de4x5_free_tx_buffs()
3669 __skb_queue_purge(&lp->cache.queue); in de4x5_free_tx_buffs()
3674 ** 'running - waiting for end of transmission' state. This means that we
3683 u_long iobase = dev->base_addr; in de4x5_save_skbs()
3686 if (!lp->cache.save_cnt) { in de4x5_save_skbs()
3693 lp->cache.save_cnt++; in de4x5_save_skbs()
3702 u_long iobase = dev->base_addr; in de4x5_rst_desc_ring()
3706 if (lp->cache.save_cnt) { in de4x5_rst_desc_ring()
3708 outl(lp->dma_rings, DE4X5_RRBA); in de4x5_rst_desc_ring()
3709 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), in de4x5_rst_desc_ring()
3712 lp->rx_new = lp->rx_old = 0; in de4x5_rst_desc_ring()
3713 lp->tx_new = lp->tx_old = 0; in de4x5_rst_desc_ring()
3715 for (i = 0; i < lp->rxRingSize; i++) { in de4x5_rst_desc_ring()
3716 lp->rx_ring[i].status = cpu_to_le32(R_OWN); in de4x5_rst_desc_ring()
3719 for (i = 0; i < lp->txRingSize; i++) { in de4x5_rst_desc_ring()
3720 lp->tx_ring[i].status = cpu_to_le32(0); in de4x5_rst_desc_ring()
3724 lp->cache.save_cnt--; in de4x5_rst_desc_ring()
3733 u_long iobase = dev->base_addr; in de4x5_cache_state()
3737 lp->cache.csr0 = inl(DE4X5_BMR); in de4x5_cache_state()
3738 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR)); in de4x5_cache_state()
3739 lp->cache.csr7 = inl(DE4X5_IMR); in de4x5_cache_state()
3743 outl(lp->cache.csr0, DE4X5_BMR); in de4x5_cache_state()
3744 outl(lp->cache.csr6, DE4X5_OMR); in de4x5_cache_state()
3745 outl(lp->cache.csr7, DE4X5_IMR); in de4x5_cache_state()
3746 if (lp->chipset == DC21140) { in de4x5_cache_state()
3747 gep_wr(lp->cache.gepc, dev); in de4x5_cache_state()
3748 gep_wr(lp->cache.gep, dev); in de4x5_cache_state()
3750 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, in de4x5_cache_state()
3751 lp->cache.csr15); in de4x5_cache_state()
3762 __skb_queue_tail(&lp->cache.queue, skb); in de4x5_put_cache()
3770 __skb_queue_head(&lp->cache.queue, skb); in de4x5_putb_cache()
3778 return __skb_dequeue(&lp->cache.queue); in de4x5_get_cache()
3783 ** is received and the auto-negotiation status is NWAY OK.
3789 u_long iobase = dev->base_addr; in test_ans()
3792 if (lp->timeout < 0) { in test_ans()
3793 lp->timeout = msec/100; in test_ans()
3804 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) { in test_ans()
3807 lp->timeout = -1; in test_ans()
3817 u_long iobase = dev->base_addr; in de4x5_setup_intr()
3836 u_long iobase = dev->base_addr; in reset_init_sia()
3839 if (lp->useSROM) { in reset_init_sia()
3840 if (lp->ibn == 3) { in reset_init_sia()
3841 srom_exec(dev, lp->phy[lp->active].rst); in reset_init_sia()
3842 srom_exec(dev, lp->phy[lp->active].gep); in reset_init_sia()
3846 csr15 = lp->cache.csr15; in reset_init_sia()
3847 csr14 = lp->cache.csr14; in reset_init_sia()
3848 csr13 = lp->cache.csr13; in reset_init_sia()
3849 outl(csr15 | lp->cache.gepc, DE4X5_SIGR); in reset_init_sia()
3850 outl(csr15 | lp->cache.gep, DE4X5_SIGR); in reset_init_sia()
3871 *buf++ = dev->dev_addr[i]; in create_packet()
3874 *buf++ = dev->dev_addr[i]; in create_packet()
3892 i = edev->id.driver_data; in EISA_signature()
3910 if (lp->chipset == DC21040) { in PCI_signature()
3913 } else { /* Search for a DEC name in the SROM */ in PCI_signature()
3914 int tmp = *((char *)&lp->srom + 19) * 3; in PCI_signature()
3915 strncpy(name, (char *)&lp->srom + 26 + tmp, 8); in PCI_signature()
3925 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" : in PCI_signature()
3926 ((lp->chipset == DC21041) ? "DC21041" : in PCI_signature()
3927 ((lp->chipset == DC21140) ? "DC21140" : in PCI_signature()
3928 ((lp->chipset == DC21142) ? "DC21142" : in PCI_signature()
3929 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN" in PCI_signature()
3932 if (lp->chipset != DC21041) { in PCI_signature()
3933 lp->useSROM = true; /* card is not recognisably DEC */ in PCI_signature()
3935 } else if ((lp->chipset & ~0x00ff) == DC2114x) { in PCI_signature()
3936 lp->useSROM = true; in PCI_signature()
3942 ** the DC21040, else read the SROM for the other chips.
3943 ** The SROM may not be present in a multi-MAC card, so first read the
3945 ** immediately with the prior srom contents intact (the h/w address will
3954 if (lp->chipset == DC21040) { in DevicePresent()
3955 if (lp->bus == EISA) { in DevicePresent()
3960 } else { /* Read new srom */ in DevicePresent()
3962 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD); in DevicePresent()
3969 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */ in DevicePresent()
3973 p = (__le16 *)&lp->srom; in DevicePresent()
3978 de4x5_dbg_srom(&lp->srom); in DevicePresent()
4005 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) { in enet_addr_rst()
4020 ** For the bad status case and no SROM, then add one to the previous
4023 ** as the first three are invariant - assigned to an organisation.
4028 u_long iobase = dev->base_addr; in get_hw_addr()
4037 if (k > 0xffff) k-=0xffff; in get_hw_addr()
4039 if (lp->bus == PCI) { in get_hw_addr()
4040 if (lp->chipset == DC21040) { in get_hw_addr()
4043 dev->dev_addr[i++] = (u_char) tmp; in get_hw_addr()
4046 dev->dev_addr[i++] = (u_char) tmp; in get_hw_addr()
4048 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++; in get_hw_addr()
4049 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++; in get_hw_addr()
4051 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++; in get_hw_addr()
4052 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++; in get_hw_addr()
4056 dev->dev_addr[i++] = (u_char) tmp; in get_hw_addr()
4058 dev->dev_addr[i++] = (u_char) tmp; in get_hw_addr()
4061 if (k > 0xffff) k-=0xffff; in get_hw_addr()
4065 if (lp->bus == PCI) { in get_hw_addr()
4066 if (lp->chipset == DC21040) { in get_hw_addr()
4071 if ((k != chksum) && (dec_only)) status = -1; in get_hw_addr()
4076 if ((k != chksum) && (dec_only)) status = -1; in get_hw_addr()
4079 /* If possible, try to fix a broken card - SMC only so far */ in get_hw_addr()
4084 ** If the address starts with 00 a0, we have to bit-reverse in get_hw_addr()
4088 (dev->dev_addr[0] == 0) && in get_hw_addr()
4089 (dev->dev_addr[1] == 0xa0) ) in get_hw_addr()
4093 int x = dev->dev_addr[i]; in get_hw_addr()
4096 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1); in get_hw_addr()
4116 if (!memcmp(&lp->srom, &enet_det[i], 3) && in de4x5_bad_srom()
4117 !memcmp((char *)&lp->srom+0x10, &enet_det[i], 3)) { in de4x5_bad_srom()
4137 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom)); in srom_repair()
4138 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN); in srom_repair()
4139 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100); in srom_repair()
4140 lp->useSROM = true; in srom_repair()
4146 ** Assume that the irq's do not follow the PCI spec - this is seems
4155 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i]; in test_bad_enet()
4157 if ((lp->chipset == last.chipset) && in test_bad_enet()
4158 (lp->bus_num == last.bus) && (lp->bus_num > 0)) { in test_bad_enet()
4159 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i]; in test_bad_enet()
4160 for (i=ETH_ALEN-1; i>2; --i) { in test_bad_enet()
4161 dev->dev_addr[i] += 1; in test_bad_enet()
4162 if (dev->dev_addr[i] != 0) break; in test_bad_enet()
4164 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i]; in test_bad_enet()
4166 dev->irq = last.irq; in test_bad_enet()
4172 last.chipset = lp->chipset; in test_bad_enet()
4173 last.bus = lp->bus_num; in test_bad_enet()
4174 last.irq = dev->irq; in test_bad_enet()
4175 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i]; in test_bad_enet()
4187 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) && in an_exception()
4188 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) { in an_exception()
4189 return -1; in an_exception()
4196 ** SROM Read
4301 if (lp->chipset == infoleaf_array[i].chipset) break; in srom_infoleaf_info()
4304 lp->useSROM = false; in srom_infoleaf_info()
4305 printk("%s: Cannot find correct chipset for SROM decoding!\n", in srom_infoleaf_info()
4306 dev->name); in srom_infoleaf_info()
4307 return -ENXIO; in srom_infoleaf_info()
4310 lp->infoleaf_fn = infoleaf_array[i].fn; in srom_infoleaf_info()
4313 count = *((u_char *)&lp->srom + 19); in srom_infoleaf_info()
4314 p = (u_char *)&lp->srom + 26; in srom_infoleaf_info()
4317 for (i=count; i; --i, p+=3) { in srom_infoleaf_info()
4318 if (lp->device == *p) break; in srom_infoleaf_info()
4321 lp->useSROM = false; in srom_infoleaf_info()
4322 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n", in srom_infoleaf_info()
4323 dev->name, lp->device); in srom_infoleaf_info()
4324 return -ENXIO; in srom_infoleaf_info()
4328 lp->infoleaf_offset = get_unaligned_le16(p + 1); in srom_infoleaf_info()
4338 ** will follow the discovery process from MII address 1-31 then 0.
4344 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; in srom_init()
4348 if (lp->chipset == DC21140) { in srom_init()
4349 lp->cache.gepc = (*p++ | GEP_CTRL); in srom_init()
4350 gep_wr(lp->cache.gepc, dev); in srom_init()
4357 for (;count; --count) { in srom_init()
4387 u_long iobase = dev->base_addr; in srom_exec()
4391 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return; in srom_exec()
4393 if (lp->chipset != DC21140) RESET_SIA; in srom_exec()
4395 while (count--) { in srom_exec()
4396 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ? in srom_exec()
4401 if (lp->chipset != DC21140) { in srom_exec()
4402 outl(lp->cache.csr14, DE4X5_STRR); in srom_exec()
4403 outl(lp->cache.csr13, DE4X5_SICR); in srom_exec()
4409 ** unless I implement the DC21041 SROM functions. There's no need
4423 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; in dc21140_infoleaf()
4430 lp->cache.gepc = (*p++ | GEP_CTRL); in dc21140_infoleaf()
4442 if (lp->tcount == count) { in dc21140_infoleaf()
4443 lp->media = NC; in dc21140_infoleaf()
4444 if (lp->media != lp->c_media) { in dc21140_infoleaf()
4446 lp->c_media = lp->media; in dc21140_infoleaf()
4448 lp->media = INIT; in dc21140_infoleaf()
4449 lp->tcount = 0; in dc21140_infoleaf()
4450 lp->tx_enable = false; in dc21140_infoleaf()
4461 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; in dc21142_infoleaf()
4477 if (lp->tcount == count) { in dc21142_infoleaf()
4478 lp->media = NC; in dc21142_infoleaf()
4479 if (lp->media != lp->c_media) { in dc21142_infoleaf()
4481 lp->c_media = lp->media; in dc21142_infoleaf()
4483 lp->media = INIT; in dc21142_infoleaf()
4484 lp->tcount = 0; in dc21142_infoleaf()
4485 lp->tx_enable = false; in dc21142_infoleaf()
4496 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; in dc21143_infoleaf()
4511 if (lp->tcount == count) { in dc21143_infoleaf()
4512 lp->media = NC; in dc21143_infoleaf()
4513 if (lp->media != lp->c_media) { in dc21143_infoleaf()
4515 lp->c_media = lp->media; in dc21143_infoleaf()
4517 lp->media = INIT; in dc21143_infoleaf()
4518 lp->tcount = 0; in dc21143_infoleaf()
4519 lp->tx_enable = false; in dc21143_infoleaf()
4536 if (--count > lp->tcount) { in compact_infoblock()
4544 if ((lp->media == INIT) && (lp->timeout < 0)) { in compact_infoblock()
4545 lp->ibn = COMPACT; in compact_infoblock()
4546 lp->active = 0; in compact_infoblock()
4547 gep_wr(lp->cache.gepc, dev); in compact_infoblock()
4548 lp->infoblock_media = (*p++) & COMPACT_MC; in compact_infoblock()
4549 lp->cache.gep = *p++; in compact_infoblock()
4553 lp->asBitValid = (flags & 0x80) ? 0 : -1; in compact_infoblock()
4554 lp->defMedium = (flags & 0x40) ? -1 : 0; in compact_infoblock()
4555 lp->asBit = 1 << ((csr6 >> 1) & 0x07); in compact_infoblock()
4556 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; in compact_infoblock()
4557 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); in compact_infoblock()
4558 lp->useMII = false; in compact_infoblock()
4576 if (--count > lp->tcount) { in type0_infoblock()
4584 if ((lp->media == INIT) && (lp->timeout < 0)) { in type0_infoblock()
4585 lp->ibn = 0; in type0_infoblock()
4586 lp->active = 0; in type0_infoblock()
4587 gep_wr(lp->cache.gepc, dev); in type0_infoblock()
4589 lp->infoblock_media = (*p++) & BLOCK0_MC; in type0_infoblock()
4590 lp->cache.gep = *p++; in type0_infoblock()
4594 lp->asBitValid = (flags & 0x80) ? 0 : -1; in type0_infoblock()
4595 lp->defMedium = (flags & 0x40) ? -1 : 0; in type0_infoblock()
4596 lp->asBit = 1 << ((csr6 >> 1) & 0x07); in type0_infoblock()
4597 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; in type0_infoblock()
4598 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); in type0_infoblock()
4599 lp->useMII = false; in type0_infoblock()
4616 if (--count > lp->tcount) { in type1_infoblock()
4625 if (lp->state == INITIALISED) { in type1_infoblock()
4626 lp->ibn = 1; in type1_infoblock()
4627 lp->active = *p++; in type1_infoblock()
4628 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1); in type1_infoblock()
4629 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1); in type1_infoblock()
4630 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2; in type1_infoblock()
4631 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2; in type1_infoblock()
4632 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2; in type1_infoblock()
4633 lp->phy[lp->active].ttm = get_unaligned_le16(p); in type1_infoblock()
4635 } else if ((lp->media == INIT) && (lp->timeout < 0)) { in type1_infoblock()
4636 lp->ibn = 1; in type1_infoblock()
4637 lp->active = *p; in type1_infoblock()
4638 lp->infoblock_csr6 = OMR_MII_100; in type1_infoblock()
4639 lp->useMII = true; in type1_infoblock()
4640 lp->infoblock_media = ANS; in type1_infoblock()
4655 if (--count > lp->tcount) { in type2_infoblock()
4663 if ((lp->media == INIT) && (lp->timeout < 0)) { in type2_infoblock()
4664 lp->ibn = 2; in type2_infoblock()
4665 lp->active = 0; in type2_infoblock()
4667 lp->infoblock_media = (*p) & MEDIA_CODE; in type2_infoblock()
4670 lp->cache.csr13 = get_unaligned_le16(p); p += 2; in type2_infoblock()
4671 lp->cache.csr14 = get_unaligned_le16(p); p += 2; in type2_infoblock()
4672 lp->cache.csr15 = get_unaligned_le16(p); p += 2; in type2_infoblock()
4674 lp->cache.csr13 = CSR13; in type2_infoblock()
4675 lp->cache.csr14 = CSR14; in type2_infoblock()
4676 lp->cache.csr15 = CSR15; in type2_infoblock()
4678 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2; in type2_infoblock()
4679 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); in type2_infoblock()
4680 lp->infoblock_csr6 = OMR_SIA; in type2_infoblock()
4681 lp->useMII = false; in type2_infoblock()
4696 if (--count > lp->tcount) { in type3_infoblock()
4705 if (lp->state == INITIALISED) { in type3_infoblock()
4706 lp->ibn = 3; in type3_infoblock()
4707 lp->active = *p++; in type3_infoblock()
4708 if (MOTO_SROM_BUG) lp->active = 0; in type3_infoblock()
4709 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1); in type3_infoblock()
4710 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1); in type3_infoblock()
4711 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2; in type3_infoblock()
4712 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2; in type3_infoblock()
4713 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2; in type3_infoblock()
4714 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2; in type3_infoblock()
4715 lp->phy[lp->active].mci = *p; in type3_infoblock()
4717 } else if ((lp->media == INIT) && (lp->timeout < 0)) { in type3_infoblock()
4718 lp->ibn = 3; in type3_infoblock()
4719 lp->active = *p; in type3_infoblock()
4720 if (MOTO_SROM_BUG) lp->active = 0; in type3_infoblock()
4721 lp->infoblock_csr6 = OMR_MII_100; in type3_infoblock()
4722 lp->useMII = true; in type3_infoblock()
4723 lp->infoblock_media = ANS; in type3_infoblock()
4738 if (--count > lp->tcount) { in type4_infoblock()
4746 if ((lp->media == INIT) && (lp->timeout < 0)) { in type4_infoblock()
4747 lp->ibn = 4; in type4_infoblock()
4748 lp->active = 0; in type4_infoblock()
4750 lp->infoblock_media = (*p++) & MEDIA_CODE; in type4_infoblock()
4751 lp->cache.csr13 = CSR13; /* Hard coded defaults */ in type4_infoblock()
4752 lp->cache.csr14 = CSR14; in type4_infoblock()
4753 lp->cache.csr15 = CSR15; in type4_infoblock()
4754 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2; in type4_infoblock()
4755 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2; in type4_infoblock()
4759 lp->asBitValid = (flags & 0x80) ? 0 : -1; in type4_infoblock()
4760 lp->defMedium = (flags & 0x40) ? -1 : 0; in type4_infoblock()
4761 lp->asBit = 1 << ((csr6 >> 1) & 0x07); in type4_infoblock()
4762 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; in type4_infoblock()
4763 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); in type4_infoblock()
4764 lp->useMII = false; in type4_infoblock()
4783 if (--count > lp->tcount) { in type5_infoblock()
4792 if ((lp->state == INITIALISED) || (lp->media == INIT)) { in type5_infoblock()
4794 lp->rst = p; in type5_infoblock()
4795 srom_exec(dev, lp->rst); in type5_infoblock()
4813 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */ in mii_rd()
4826 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */ in mii_wr()
4875 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */ in mii_ta()
4964 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
4970 u_long iobase = dev->base_addr; in mii_get_phy()
4974 lp->active = 0; in mii_get_phy()
4975 lp->useMII = true; in mii_get_phy()
4978 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) { in mii_get_phy()
4979 lp->phy[lp->active].addr = i; in mii_get_phy()
4986 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++); in mii_get_phy()
4988 memcpy((char *)&lp->phy[k], in mii_get_phy()
4990 lp->phy[k].addr = i; in mii_get_phy()
4991 lp->mii_cnt++; in mii_get_phy()
4992 lp->active++; in mii_get_phy()
4999 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++); in mii_get_phy()
5000 lp->phy[k].addr = i; in mii_get_phy()
5001 lp->phy[k].id = id; in mii_get_phy()
5002 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */ in mii_get_phy()
5003 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */ in mii_get_phy()
5004 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */ in mii_get_phy()
5005 lp->mii_cnt++; in mii_get_phy()
5006 lp->active++; in mii_get_phy()
5007 …ntrol. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev->name); in mii_get_phy()
5016 lp->active = 0; in mii_get_phy()
5017 if (lp->phy[0].id) { /* Reset the PHY devices */ in mii_get_phy()
5018 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/ in mii_get_phy()
5019 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII); in mii_get_phy()
5020 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST); in mii_get_phy()
5025 if (!lp->mii_cnt) lp->useMII = false; in mii_get_phy()
5027 return lp->mii_cnt; in mii_get_phy()
5031 build_setup_frame(struct net_device *dev, int mode) in build_setup_frame() argument
5035 char *pa = lp->setup_frame; in build_setup_frame()
5038 if (mode == ALL) { in build_setup_frame()
5039 memset(lp->setup_frame, 0, SETUP_FRAME_LEN); in build_setup_frame()
5042 if (lp->setup_f == HASH_PERF) { in build_setup_frame()
5043 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) { in build_setup_frame()
5044 *(pa + i) = dev->dev_addr[i]; /* Host address */ in build_setup_frame()
5047 *(lp->setup_frame + (DE4X5_HASH_TABLE_LEN >> 3) - 3) = 0x80; in build_setup_frame()
5050 *(pa + (i&1)) = dev->dev_addr[i]; in build_setup_frame()
5066 del_timer_sync(&lp->timer); in disable_ast()
5073 u_long iobase = dev->base_addr; in de4x5_switch_mac_port()
5081 omr |= lp->infoblock_csr6; in de4x5_switch_mac_port()
5088 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */ in de4x5_switch_mac_port()
5089 if (lp->chipset == DC21140) { in de4x5_switch_mac_port()
5090 gep_wr(lp->cache.gepc, dev); in de4x5_switch_mac_port()
5091 gep_wr(lp->cache.gep, dev); in de4x5_switch_mac_port()
5092 } else if ((lp->chipset & ~0x0ff) == DC2114x) { in de4x5_switch_mac_port()
5093 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15); in de4x5_switch_mac_port()
5109 u_long iobase = dev->base_addr; in gep_wr()
5111 if (lp->chipset == DC21140) { in gep_wr()
5113 } else if ((lp->chipset & ~0x00ff) == DC2114x) { in gep_wr()
5114 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR); in gep_wr()
5122 u_long iobase = dev->base_addr; in gep_rd()
5124 if (lp->chipset == DC21140) { in gep_rd()
5126 } else if ((lp->chipset & ~0x00ff) == DC2114x) { in gep_rd()
5137 u_long iobase = dev->base_addr; in yawn()
5139 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return; in yawn()
5141 if(lp->bus == EISA) { in yawn()
5158 struct pci_dev *pdev = to_pci_dev (lp->gendev); in yawn()
5183 lp->params.fdx = false; in de4x5_parse_params()
5184 lp->params.autosense = AUTO; in de4x5_parse_params()
5188 if ((p = strstr(args, dev->name))) { in de4x5_parse_params()
5189 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p); in de4x5_parse_params()
5193 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = true; in de4x5_parse_params()
5197 lp->params.autosense = TP_NW; in de4x5_parse_params()
5199 lp->params.autosense = TP; in de4x5_parse_params()
5201 lp->params.autosense = BNC; in de4x5_parse_params()
5203 lp->params.autosense = BNC; in de4x5_parse_params()
5205 lp->params.autosense = AUI; in de4x5_parse_params()
5207 lp->params.autosense = _10Mb; in de4x5_parse_params()
5209 lp->params.autosense = _100Mb; in de4x5_parse_params()
5211 lp->params.autosense = AUTO; in de4x5_parse_params()
5225 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq); in de4x5_dbg_open()
5226 printk("\tphysical address: %pM\n", dev->dev_addr); in de4x5_dbg_open()
5228 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring); in de4x5_dbg_open()
5230 for (i=0;i<lp->rxRingSize-1;i++){ in de4x5_dbg_open()
5232 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status); in de4x5_dbg_open()
5235 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status); in de4x5_dbg_open()
5237 for (i=0;i<lp->txRingSize-1;i++){ in de4x5_dbg_open()
5239 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status); in de4x5_dbg_open()
5242 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status); in de4x5_dbg_open()
5244 for (i=0;i<lp->rxRingSize-1;i++){ in de4x5_dbg_open()
5246 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf)); in de4x5_dbg_open()
5249 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf)); in de4x5_dbg_open()
5251 for (i=0;i<lp->txRingSize-1;i++){ in de4x5_dbg_open()
5253 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf)); in de4x5_dbg_open()
5256 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf)); in de4x5_dbg_open()
5258 (short)lp->rxRingSize, in de4x5_dbg_open()
5259 (short)lp->txRingSize); in de4x5_dbg_open()
5267 u_long iobase = dev->base_addr; in de4x5_dbg_mii()
5270 printk("\nMII device address: %d\n", lp->phy[k].addr); in de4x5_dbg_mii()
5271 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5272 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5273 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5274 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5275 if (lp->phy[k].id != BROADCOM_T4) { in de4x5_dbg_mii()
5276 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5277 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5279 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5280 if (lp->phy[k].id != BROADCOM_T4) { in de4x5_dbg_mii()
5281 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5282 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5284 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII)); in de4x5_dbg_mii()
5294 if (lp->media != lp->c_media) { in de4x5_dbg_media()
5296 printk("%s: media is %s%s\n", dev->name, in de4x5_dbg_media()
5297 (lp->media == NC ? "unconnected, link down or incompatible connection" : in de4x5_dbg_media()
5298 (lp->media == TP ? "TP" : in de4x5_dbg_media()
5299 (lp->media == ANS ? "TP/Nway" : in de4x5_dbg_media()
5300 (lp->media == BNC ? "BNC" : in de4x5_dbg_media()
5301 (lp->media == AUI ? "AUI" : in de4x5_dbg_media()
5302 (lp->media == BNC_AUI ? "BNC/AUI" : in de4x5_dbg_media()
5303 (lp->media == EXT_SIA ? "EXT SIA" : in de4x5_dbg_media()
5304 (lp->media == _100Mb ? "100Mb/s" : in de4x5_dbg_media()
5305 (lp->media == _10Mb ? "10Mb/s" : in de4x5_dbg_media()
5307 ))))))))), (lp->fdx?" full duplex.":".")); in de4x5_dbg_media()
5309 lp->c_media = lp->media; in de4x5_dbg_media()
5319 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id)); in de4x5_dbg_srom()
5320 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id)); in de4x5_dbg_srom()
5321 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc)); in de4x5_dbg_srom()
5322 printk("SROM version: %02x\n", (u_char)(p->version)); in de4x5_dbg_srom()
5323 printk("# controllers: %02x\n", (u_char)(p->num_controllers)); in de4x5_dbg_srom()
5325 printk("Hardware Address: %pM\n", p->ieee_addr); in de4x5_dbg_srom()
5326 printk("CRC checksum: %04x\n", (u_short)(p->chksum)); in de4x5_dbg_srom()
5339 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n", in de4x5_dbg_rx()
5340 skb->data, &skb->data[6], in de4x5_dbg_rx()
5341 (u_char)skb->data[12], in de4x5_dbg_rx()
5342 (u_char)skb->data[13], in de4x5_dbg_rx()
5344 for (j=0; len>0;j+=16, len-=16) { in de4x5_dbg_rx()
5347 printk("%02x ",(u_char)skb->data[i+j]); in de4x5_dbg_rx()
5363 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru; in de4x5_ioctl()
5364 u_long iobase = dev->base_addr; in de4x5_ioctl()
5374 switch(ioc->cmd) { in de4x5_ioctl()
5376 ioc->len = ETH_ALEN; in de4x5_ioctl()
5378 tmp.addr[i] = dev->dev_addr[i]; in de4x5_ioctl()
5380 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; in de4x5_ioctl()
5384 if (!capable(CAP_NET_ADMIN)) return -EPERM; in de4x5_ioctl()
5385 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT; in de4x5_ioctl()
5387 return -EBUSY; in de4x5_ioctl()
5390 dev->dev_addr[i] = tmp.addr[i]; in de4x5_ioctl()
5394 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET | in de4x5_ioctl()
5396 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize; in de4x5_ioctl()
5402 if (!capable(CAP_NET_ADMIN)) return -EPERM; in de4x5_ioctl()
5403 printk("%s: Boo!\n", dev->name); in de4x5_ioctl()
5407 if (!capable(CAP_NET_ADMIN)) return -EPERM; in de4x5_ioctl()
5416 ioc->len = sizeof(statbuf); in de4x5_ioctl()
5417 spin_lock_irqsave(&lp->lock, flags); in de4x5_ioctl()
5418 memcpy(&statbuf, &lp->pktStats, ioc->len); in de4x5_ioctl()
5419 spin_unlock_irqrestore(&lp->lock, flags); in de4x5_ioctl()
5420 if (copy_to_user(ioc->data, &statbuf, ioc->len)) in de4x5_ioctl()
5421 return -EFAULT; in de4x5_ioctl()
5425 if (!capable(CAP_NET_ADMIN)) return -EPERM; in de4x5_ioctl()
5426 spin_lock_irqsave(&lp->lock, flags); in de4x5_ioctl()
5427 memset(&lp->pktStats, 0, sizeof(lp->pktStats)); in de4x5_ioctl()
5428 spin_unlock_irqrestore(&lp->lock, flags); in de4x5_ioctl()
5433 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT; in de4x5_ioctl()
5437 if (!capable(CAP_NET_ADMIN)) return -EPERM; in de4x5_ioctl()
5438 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT; in de4x5_ioctl()
5452 ioc->len = j; in de4x5_ioctl()
5453 if (copy_to_user(ioc->data, tmp.lval, ioc->len)) in de4x5_ioctl()
5454 return -EFAULT; in de4x5_ioctl()
5461 tmp.addr[j++] = dev->irq; in de4x5_ioctl()
5463 tmp.addr[j++] = dev->dev_addr[i]; in de4x5_ioctl()
5465 tmp.addr[j++] = lp->rxRingSize; in de4x5_ioctl()
5466 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4; in de4x5_ioctl()
5467 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4; in de4x5_ioctl()
5469 for (i=0;i<lp->rxRingSize-1;i++){ in de4x5_ioctl()
5471 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4; in de4x5_ioctl()
5474 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4; in de4x5_ioctl()
5475 for (i=0;i<lp->txRingSize-1;i++){ in de4x5_ioctl()
5477 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4; in de4x5_ioctl()
5480 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4; in de4x5_ioctl()
5482 for (i=0;i<lp->rxRingSize-1;i++){ in de4x5_ioctl()
5484 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4; in de4x5_ioctl()
5487 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4; in de4x5_ioctl()
5488 for (i=0;i<lp->txRingSize-1;i++){ in de4x5_ioctl()
5490 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4; in de4x5_ioctl()
5493 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4; in de4x5_ioctl()
5495 for (i=0;i<lp->rxRingSize;i++){ in de4x5_ioctl()
5496 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4; in de4x5_ioctl()
5498 for (i=0;i<lp->txRingSize;i++){ in de4x5_ioctl()
5499 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4; in de4x5_ioctl()
5510 tmp.lval[j>>2] = lp->chipset; j+=4; in de4x5_ioctl()
5511 if (lp->chipset == DC21140) { in de4x5_ioctl()
5519 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4; in de4x5_ioctl()
5520 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) { in de4x5_ioctl()
5521 tmp.lval[j>>2] = lp->active; j+=4; in de4x5_ioctl()
5522 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_ioctl()
5523 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_ioctl()
5524 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_ioctl()
5525 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_ioctl()
5526 if (lp->phy[lp->active].id != BROADCOM_T4) { in de4x5_ioctl()
5527 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_ioctl()
5528 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_ioctl()
5530 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_ioctl()
5531 if (lp->phy[lp->active].id != BROADCOM_T4) { in de4x5_ioctl()
5532 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_ioctl()
5533 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_ioctl()
5535 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4; in de4x5_ioctl()
5539 tmp.addr[j++] = lp->txRingSize; in de4x5_ioctl()
5542 ioc->len = j; in de4x5_ioctl()
5543 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; in de4x5_ioctl()
5548 return -EOPNOTSUPP; in de4x5_ioctl()