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/qemu/hw/m68k/
H A Dan5206.c47 MemoryRegion *sram = g_new(MemoryRegion, 1); in an5206_init() local
61 /* Internal SRAM. */ in an5206_init()
62 memory_region_init_ram(sram, NULL, "an5206.sram", 512, &error_fatal); in an5206_init()
63 memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram); in an5206_init()
H A Dmcf5208.c289 MemoryRegion *sram = g_new(MemoryRegion, 1); in mcf5208evb_init() local
305 /* Internal SRAM. */ in mcf5208evb_init()
306 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal); in mcf5208evb_init()
307 memory_region_add_subregion(address_space_mem, 0x80000000, sram); in mcf5208evb_init()
/qemu/include/hw/arm/
H A Dallwinner-a10.h60 * downloaded code to internal SRAM. After loading the SoC
61 * begins executing the code written to SRAM.
65 * the start of the first internal SRAM memory.
H A Darmsse.h34 * more SRAM banks with associated MPCs
51 * address of each SRAM bank (and thus the total amount of internal SRAM)
140 #error Too many SRAM banks
203 MemoryRegion sram[MAX_SRAM_BANKS]; member
H A Dallwinner-r40.h144 * downloaded code to internal SRAM. After loading the SoC
145 * begins executing the code written to SRAM.
149 * the start of the first internal SRAM memory.
H A Dallwinner-h3.h160 * downloaded code to internal SRAM. After loading the SoC
161 * begins executing the code written to SRAM.
165 * the start of the first internal SRAM memory.
H A Dnrf51_soc.h42 MemoryRegion sram; member
H A Dstm32f100_soc.h53 MemoryRegion sram; member
/qemu/target/avr/
H A Dtranslate.c1488 * be used towards internal SRAM. The data location is pointed to by the Z (16
1493 * instruction is especially suited for clearing status bits stored in SRAM.
1573 * Loads one byte from the data space to a register. For parts with SRAM,
1574 * the data space consists of the Register File, I/O memory and internal SRAM
1575 * (and external SRAM if applicable). For parts without SRAM, the data space
1600 * with SRAM, the data space consists of the Register File, I/O memory and
1601 * internal SRAM (and external SRAM if applicable). For parts without SRAM, the
1657 * to a register. For parts with SRAM, the data space consists of the Register
1658 * File, I/O memory and internal SRAM (and external SRAM if applicable). For
1659 * parts without SRAM, the data space consists of the Register File only. In
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/qemu/hw/arm/
H A Daspeed_ast10x0.c220 /* Internal SRAM */ in aspeed_soc_ast1030_realize()
221 sram_name = g_strdup_printf("aspeed.sram.%d", in aspeed_soc_ast1030_realize()
223 memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err); in aspeed_soc_ast1030_realize()
230 &s->sram); in aspeed_soc_ast1030_realize()
231 memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram", in aspeed_soc_ast1030_realize()
248 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram), in aspeed_soc_ast1030_realize()
338 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), in aspeed_soc_ast1030_realize()
352 OBJECT(&s->sram), &error_abort); in aspeed_soc_ast1030_realize()
369 object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram), in aspeed_soc_ast1030_realize()
H A Dstm32f100_soc.c110 /* Init SRAM region */ in stm32f100_soc_realize()
111 memory_region_init_ram(&s->sram, NULL, "STM32F100.sram", SRAM_SIZE, in stm32f100_soc_realize()
113 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); in stm32f100_soc_realize()
H A Dnrf51_soc.c94 if (!memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size, in nrf51_soc_realize()
98 memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram); in nrf51_soc_realize()
214 DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
H A Dstm32f205_soc.c124 memory_region_init_ram(&s->sram, NULL, "STM32F205.sram", SRAM_SIZE, in stm32f205_soc_realize()
126 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); in stm32f205_soc_realize()
H A Dimx25_pdk.c43 * 0xb0000000-0xb1ffffff SRAM IGNORED
44 * 0xb2000000-0xb3ffffff SRAM IGNORED
H A Dallwinner-r40.c407 /* SRAM */ in allwinner_r40_realize()
411 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1", in allwinner_r40_realize()
413 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2", in allwinner_r40_realize()
415 memory_region_init_ram(&s->sram_a3, OBJECT(dev), "sram A3", in allwinner_r40_realize()
417 memory_region_init_ram(&s->sram_a4, OBJECT(dev), "sram A4", in allwinner_r40_realize()
H A Dstm32f405_soc.c137 memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE, in stm32f405_soc_realize()
143 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram); in stm32f405_soc_realize()
/qemu/docs/system/arm/
H A Dstellaris.rst9 - 64k Flash and 8k SRAM.
21 - 256k Flash and 64k SRAM.
H A Dmusicpal.rst9 - 32 MB RAM, 256 KB SRAM, 8 MB flash.
H A Dxlnx-zynq.rst17 - SMC SRAM@0xe2000000 64MB
/qemu/hw/avr/
H A Datmega.c244 * SRAM in atmega_realize()
255 memory_region_init_ram(&s->sram, OBJECT(dev), "sram", mc->sram_size, in atmega_realize()
258 OFFSET_DATA + mc->io_size, &s->sram); in atmega_realize()
263 memory_region_init_ram_device_ptr(&s->sram_io, OBJECT(dev), "sram-as-io", in atmega_realize()
269 memory_region_init_ram(&s->sram, OBJECT(dev), "sram", in atmega_realize()
272 OFFSET_DATA + TARGET_PAGE_SIZE, &s->sram); in atmega_realize()
H A Datmega.h43 MemoryRegion sram; member
/qemu/include/hw/misc/
H A Dallwinner-sramc.h2 * Allwinner SRAM controller emulation
55 * Allwinner SRAM Controller class-level struct.
/qemu/hw/misc/
H A Dallwinner-sramc.c2 * Allwinner R40 SRAM controller emulation
37 REG_SRAM_CTL1_CFG = 0x04, /* SRAM Control register 1 */
38 REG_SRAM_VER = 0x24, /* SRAM Version register */
/qemu/include/hw/ppc/
H A Dpnv_xive.h79 * These are in a SRAM protected by ECC.
151 * These are in a SRAM protected by ECC.
/qemu/hw/sh4/
H A Dsh7750_regs.h552 #define SH7750_BCR1_A0MPX 0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX) */
561 #define SH7750_BCR1_A1MBC 0x00200000 /* Area 1 SRAM Byte Control Mode: */
562 /* 0 - Area 1 SRAM is set to */
564 /* 1 - Area 1 SRAM is set to byte */
566 #define SH7750_BCR1_A4MBC 0x00100000 /* Area 4 SRAM Byte Control Mode: */
567 /* 0 - Area 4 SRAM is set to */
569 /* 1 - Area 4 SRAM is set to byte */
580 /* 0 - SRAM/burst ROM interface */
598 #define SH7750_BCR1_A0BST_SRAM 0x0000 /* Area 0 accessed as SRAM i/f */
609 #define SH7750_BCR1_A5BST_SRAM 0x0000 /* Area 5 accessed as SRAM i/f */
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