Searched +full:spi +full:- +full:nor (Results 1 – 10 of 10) sorted by relevance
4 SiFive HiFive Unleashed Development Board is the ultimate RISC-V development5 board featuring the Freedom U540 multi-core RISC-V processor.8 -----------------15 * Platform-Level Interrupt Controller (PLIC)17 * L2 Loosely Integrated Memory (L2-LIM)22 * 1 One-Time Programmable (OTP) memory with stored serial number26 * 1 SD card in SPI mode30 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.32 is also possible to create a 32-bit variant with the same peripherals except33 that the RISC-V cores are replaced by the 32-bit ones (E31 and U34), to help[all …]
4 * Copyright (c) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>15 #include "hw/arm/fsl-imx6.h"18 #include "hw/qdev-properties.h"19 #include "qemu/error-report.h"26 .board_id = -1,46 if (machine->ram_size > FSL_IMX6_MMDC_SIZE) { in sabrelite_init()48 machine->ram_size, FSL_IMX6_MMDC_SIZE); in sabrelite_init()56 object_property_set_int(OBJECT(s), "fec-phy-num", 6, &error_fatal); in sabrelite_init()61 machine->ram); in sabrelite_init()65 * TODO: Ideally we would expose the chip select and spi bus on the in sabrelite_init()[all …]
28 #include "hw/adc/zynq-xadc.h"31 #include "qemu/error-report.h"36 #include "hw/qdev-clock.h"41 #include "target/arm/cpu-qom.h"44 #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")112 rom_add_blob_fixed("board-setup", board_setup_blob, in zynq_write_board_setup()125 object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); in gem_init()138 SSIBus *spi; in zynq_init_spi_flashes() local144 dev = qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); in zynq_init_spi_flashes()145 qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); in zynq_init_spi_flashes()[all …]
1 Xilinx Zynq board (``xilinx-zynq-a9``)4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual10 QEMU xilinx-zynq-a9 board supports following devices:11 - A9 MPCORE12 - cortex-a913 - GIC v114 - Generic timer15 - wdt16 - OCM 256KB[all …]
2 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu15 * 5) OTP (One-Time Programmable) memory with stored serial number18 * 8) SPI0 connected to an SPI flash39 #include "qemu/error-report.h"99 uint64_t mem_size = ms->ram_size; in create_fdt()111 "sifive,plic-1.0.0", "riscv,plic0" in create_fdt()114 fdt = ms->fdt = create_device_tree(&s->fdt_size); in create_fdt()122 "sifive,hifive-unleashed-a00"); in create_fdt()123 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); in create_fdt()[all …]
2 * QEMU PowerPC SPI model6 * SPDX-License-Identifier: GPL-2.0-or-later11 #include "hw/qdev-properties.h"46 uint16_t rdr_match_mask = GETFIELD(SPI_MM_RDR_MATCH_MASK, s->regs[SPI_MM_REG]); in does_rdr_match()47 uint16_t rdr_match_val = GETFIELD(SPI_MM_RDR_MATCH_VAL, s->regs[SPI_MM_REG]); in does_rdr_match()50 GETFIELD(PPC_BITMASK(48, 63), s->regs[SPI_RCV_DATA_REG]))) { in does_rdr_match()61 * Offset is an index between 0 and PNV_SPI_REG_SIZE - 1 in get_from_offset()65 byte = (s->regs[SPI_XMIT_DATA_REG] >> (56 - offset * 8)) & 0xFF; in get_from_offset()89 } else if (!fifo8_is_empty(&s->rx_fifo)) { in read_from_frame()90 byte = fifo8_pop(&s->rx_fifo); in read_from_frame()[all …]
2 * ST M25P80 emulator. Emulate all SPI flash devices based on the m25p80 command26 #include "system/block-backend.h"29 #include "hw/qdev-properties.h"30 #include "hw/qdev-properties-system.h"36 #include "qemu/error-report.h"46 /* Fields for FlashPartInfo->flags */74 * Big sized spi nor are often stacked devices, thus sometime178 /* Atmel -- some are (confusingly) marketed as "DataFlash" */194 * Atmel EEPROMS - it is assumed, that don't care bit in command197 { INFO("at25128a-nonjedec", 0x0, 0, 1, 131072, EEPROM) },[all …]
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1 /*-4 * Copyright (c) 2000-2010, LSI Logic Corporation and its contributors.17 * 3. Neither the name of the LSI Logic Corporation nor the names of its269 /* SCSIIO Reply = SPI & FCP, initiator values */287 /* For use by SCSI Initiator and SCSI Target end-to-end data protection*/469 /* SCSI IO Reply SCSIStatus values (SAM-2 status codes) */497 /* (FCP-1 RSP_CODE values and SPI-3 Packetized Failure codes) */683 uint16_t Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */
10 consult qemu-devel and not any specific individual privately.23 W: Web-page with status/info59 ------------------------------63 L: qemu-devel@nongnu.org72 R: Philippe Mathieu-Daudé <philmd@linaro.org>75 F: docs/devel/build-environment.rst76 F: docs/devel/code-of-conduct.rst78 F: docs/devel/conflict-resolution.rst80 F: docs/devel/submitting-a-patch.rst81 F: docs/devel/submitting-a-pull-request.rst[all …]