| /linux-6.8/Documentation/devicetree/bindings/perf/ |
| D | spe-pmu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
10 - Will Deacon <will@kernel.org>
14 performance sample data using an in-memory trace buffer.
18 const: arm,statistical-profiling-extension-v1
23 The PPI to signal SPE events. For heterogeneous systems where SPE is only
24 supported on a subset of the CPUs, please consult the arm,gic-v3 binding
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| /linux-6.8/tools/perf/Documentation/ |
| D | perf-arm-spe.txt | 1 perf-arm-spe(1)
5 ----
6 perf-arm-spe - Support for Arm Statistical Profiling Extension within Perf tools
9 --------
11 'perf record' -e arm_spe//
14 -----------
16 The SPE (Statistical Profiling Extension) feature provides accurate attribution of latencies and
17 events down to individual instructions. Rather than being interrupt-driven, it picks an
32 This is chosen from a sample population, for SPE this is an IMPLEMENTATION DEFINED choice of all
33 architectural instructions or all micro-ops. Sampling happens at a programmable interval. The
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| D | perf-c2c.txt | 1 perf-c2c(1)
5 ----
6 perf-c2c - Shared Data C2C/HITM Analyzer.
9 --------
12 'perf c2c record' [<options>] \-- [<record command options>] <command>
16 -----------
24 with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware
25 limitations, perf c2c is not supported on Zen3 cpus). On Arm64 it uses SPE to
27 required. See linkperf:perf-arm-spe[1] for a setup guide. Due to the
28 statistical nature of Arm SPE sampling, not every memory operation will be
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| D | perf.txt | 5 ----
6 perf - Performance analysis tools for Linux
9 --------
11 'perf' [--version] [--help] [OPTIONS] COMMAND [ARGS]
14 -------
15 -h::
16 --help::
19 -v::
20 --version::
23 -vv::
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| D | perf-record.txt | 1 perf-record(1)
5 ----
6 perf-record - Run a command and record its profile into perf.data
9 --------
11 'perf record' [-e <EVENT> | --event=EVENT] [-a] <command>
12 'perf record' [-e <EVENT> | --event=EVENT] [-a] \-- <command> [<options>]
15 -----------
17 from it, into perf.data - without displaying anything.
23 -------
27 -e::
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| /linux-6.8/tools/perf/arch/arm/util/ |
| D | pmu.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight-pmu.h>
12 #include "arm-spe.h"
13 #include "hisi-ptt.h"
14 #include "../../../util/pmu.h"
15 #include "../../../util/cs-etm.h"
17 void perf_pmu__arch_init(struct perf_pmu *pmu __maybe_unused) in perf_pmu__arch_init()
20 if (!strcmp(pmu->name, CORESIGHT_ETM_PMU_NAME)) { in perf_pmu__arch_init()
22 pmu->selectable = true; in perf_pmu__arch_init()
23 pmu->perf_event_attr_init_default = cs_etm_get_default_config; in perf_pmu__arch_init()
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| D | auxtrace.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/coresight-pmu.h>
16 #include "../../../util/pmu.h"
18 #include "cs-etm.h"
19 #include "arm-spe.h"
20 #include "hisi-ptt.h"
32 *err = -ENOMEM; in find_all_arm_spe_pmus()
40 *err = -ENOMEM; in find_all_arm_spe_pmus()
48 arm_spe_pmus[*nr_spes]->type, in find_all_arm_spe_pmus()
49 arm_spe_pmus[*nr_spes]->name); in find_all_arm_spe_pmus()
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| /linux-6.8/arch/arm64/kvm/hyp/nvhe/ |
| D | switch.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 - ARM Ltd
8 #include <hyp/sysreg-sr.h>
10 #include <linux/arm-smccc.h>
26 #include <asm/debug-monitors.h>
32 /* Non-VHE specific context */
46 val = vcpu->arch.cptr_el2; in __activate_traps()
70 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; in __activate_traps()
109 write_sysreg(this_cpu_ptr(&kvm_init_params)->hcr_el2, hcr_el2); in __deactivate_traps()
115 /* Save VGICv3 state on non-VHE systems */
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| D | pkvm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
39 * Linux guests assume support for floating-point and Advanced SIMD. Do in pvm_init_traps_aa64pfr0()
71 vcpu->arch.hcr_el2 |= hcr_set; in pvm_init_traps_aa64pfr0()
72 vcpu->arch.hcr_el2 &= ~hcr_clear; in pvm_init_traps_aa64pfr0()
73 vcpu->arch.cptr_el2 |= cptr_set; in pvm_init_traps_aa64pfr0()
74 vcpu->arch.cptr_el2 &= ~cptr_clear; in pvm_init_traps_aa64pfr0()
92 vcpu->arch.hcr_el2 |= hcr_set; in pvm_init_traps_aa64pfr1()
93 vcpu->arch.hcr_el2 &= ~hcr_clear; in pvm_init_traps_aa64pfr1()
106 /* Trap/constrain PMU */ in pvm_init_traps_aa64dfr0()
121 /* Trap SPE */ in pvm_init_traps_aa64dfr0()
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| /linux-6.8/drivers/perf/ |
| D | arm_pmu_acpi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 gsi = gicc->performance_interrupt; in arm_pmu_acpi_register_irq()
32 * Per the ACPI spec, the MADT cannot describe a PMU that doesn't in arm_pmu_acpi_register_irq()
41 if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE) in arm_pmu_acpi_register_irq()
67 gsi = gicc->performance_interrupt; in arm_pmu_acpi_unregister_irq()
83 if (pdev->num_resources != 1) in arm_acpi_register_pmu_device()
84 return -ENXIO; in arm_acpi_register_pmu_device()
86 if (pdev->resource[0].flags != IORESOURCE_IRQ) in arm_acpi_register_pmu_device()
87 return -ENXIO; in arm_acpi_register_pmu_device()
97 if (gicc->header.length < len) in arm_acpi_register_pmu_device()
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| D | arm_spe_pmu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
54 event->hw.flags |= SPE_PMU_HW_FLAGS_CX; in set_spe_event_has_cx()
59 return !!(event->hw.flags & SPE_PMU_HW_FLAGS_CX); in get_spe_event_has_cx()
71 struct pmu pmu; member
96 #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu))
98 /* Convert a free-running index from perf into an SPE buffer offset */
99 #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
127 return !!(spe_pmu->features & arm_spe_pmu_feat_caps[cap]); in arm_spe_pmu_cap_get()
131 return spe_pmu->counter_sz; in arm_spe_pmu_cap_get()
133 return spe_pmu->min_period; in arm_spe_pmu_cap_get()
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| /linux-6.8/tools/perf/arch/arm64/util/ |
| D | Build | 1 perf-y += header.o
2 perf-y += machine.o
3 perf-y += perf_regs.o
4 perf-y += tsc.o
5 perf-y += pmu.o
6 perf-$(CONFIG_LIBTRACEEVENT) += kvm-stat.o
7 perf-$(CONFIG_DWARF) += dwarf-regs.o
8 perf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
9 perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
11 perf-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o \
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| D | arm-spe.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arm Statistical Profiling Extensions (SPE) support
4 * Copyright (c) 2017-2018, Arm Ltd.
21 #include "../../../util/pmu.h"
25 #include "../../../util/arm-spe.h"
53 struct perf_pmu *arm_spe_pmu = sper->arm_spe_pmu; in arm_spe_info_fill()
56 return -EINVAL; in arm_spe_info_fill()
58 if (!session->evlist->core.nr_mmaps) in arm_spe_info_fill()
59 return -EINVAL; in arm_spe_info_fill()
61 auxtrace_info->type = PERF_AUXTRACE_ARM_SPE; in arm_spe_info_fill()
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| /linux-6.8/arch/powerpc/platforms/ |
| D | Kconfig.cputype | 1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
282 default "-mtune=power10" if $(cc-option,-mtune=power10)
283 default "-mtune=power9" if $(cc-option,-mtune=power9)
284 default "-mtune=power8" if $(cc-option,-mtune=power8)
366 This option enables kernel support for larger than 32-bit physical
371 is platform-dependent.
387 any affect on a non-altivec cpu (it does, however add code to the
403 VSX (P7 and above), but does not have any affect on a non-VSX
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| /linux-6.8/tools/perf/util/ |
| D | Build | 4 perf-y += arm64-frame-pointer-unwind-support.o
5 perf-y += addr_location.o
6 perf-y += annotate.o
7 perf-y += block-info.o
8 perf-y += block-range.o
9 perf-y += build-id.o
10 perf-y += cacheline.o
11 perf-y += config.o
12 perf-y += copyfile.o
13 perf-y += ctype.o
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| D | arm-spe.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Arm Statistical Profiling Extensions (SPE) support
4 * Copyright (c) 2017-2018, Arm Ltd.
28 #include "thread-stack.h"
31 #include "util/synthetic-events.h"
33 #include "arm-spe.h"
34 #include "arm-spe-decoder/arm-spe-decoder.h"
35 #include "arm-spe-decoder/arm-spe-pkt-decoder.h"
84 struct arm_spe *spe; member
101 static void arm_spe_dump(struct arm_spe *spe __maybe_unused, in arm_spe_dump()
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| D | auxtrace.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (c) 2013-2015, Intel Corporation.
60 #define AUXTRACE_ERR_FLG_OVERFLOW (1 << ('o' - 'a'))
61 #define AUXTRACE_ERR_FLG_DATA_LOST (1 << ('l' - 'a'))
63 #define AUXTRACE_LOG_FLG_ALL_PERF_EVTS (1 << ('a' - 'a'))
64 #define AUXTRACE_LOG_FLG_ON_ERROR (1 << ('e' - 'a'))
65 #define AUXTRACE_LOG_FLG_USE_STDOUT (1 << ('o' - 'a'))
68 * struct itrace_synth_opts - AUX area tracing synthesis options.
78 * (branch misses only for Arm SPE)
104 * @vm_tm_corr_dry_run: VM Time Correlation dry-run
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| /linux-6.8/arch/powerpc/include/asm/ |
| D | cell-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * on-chip system devices (memory controller, IO controller, etc...)
19 #include <asm/cell-pmu.h>
43 u8 spe[8]; member
50 u32 spe; member
61 u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
65 u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
73 u8 pad_0x0128_0x0400 [0x0400 - 0x0128]; /* 0x0128 */
83 u8 pad_0x0480_0x0800 [0x0800 - 0x0480]; /* 0x0480 */
111 u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */
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| /linux-6.8/include/linux/perf/ |
| D | arm_pmu.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/include/asm/pmu.h
20 * The ARMv7 CPU PMU supports up to 32 event counters.
25 * ARM PMU hw_event flags
40 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
43 [0 ... C(MAX) - 1] = { \
44 [0 ... C(OP_MAX) - 1] = { \
45 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
49 /* The events for a given PMU register set. */
52 * The events that are active on the PMU for the given index.
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| /linux-6.8/arch/arm64/include/asm/ |
| D | el2_setup.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
11 #error Assembly-only header
17 #include <linux/irqchip/arm-gic-v3.h>
42 * Allow Non-secure EL1 and EL0 to access physical timer and counter.
64 b.lt .Lskip_pmu_\@ // Skip if no PMU present
68 csel x2, xzr, x0, lt // all PMU counters from EL1
72 cbz x0, .Lskip_spe_\@ // Skip if SPE not present
74 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2,
111 /* Stage-2 translation */
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| D | kvm_host.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
14 #include <linux/arm-smccc.h>
43 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1)
61 * Mode of operation configurable with kvm-arm.mode early param.
62 * See Documentation/admin-guide/kernel-parameters.txt for more information.
94 *p = mc->head; in push_hyp_memcache()
95 mc->head = to_pa(p); in push_hyp_memcache()
96 mc->nr_pages++; in push_hyp_memcache()
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| /linux-6.8/arch/arm64/boot/dts/arm/ |
| D | foundation-v8.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
31 #address-cells = <2>;
32 #size-cells = <0>;
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| D | fvp-base-revc.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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| /linux-6.8/drivers/ps3/ |
| D | ps3-lpm.c | 1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <asm/cell-pmu.h>
66 * struct ps3_lpm_shadow_regs - Performance monitor shadow registers.
73 * The logical performance monitor provides a write-only interface to
91 * struct ps3_lpm_priv - Private lpm device data.
137 * lpm_priv - Static instance of the lpm data.
148 BUG_ON(!lpm_priv || !lpm_priv->sbd); in sbd_core()
149 return &lpm_priv->sbd->core; in sbd_core()
153 * use_start_stop_bookmark - Enable the PPU bookmark trace.
192 * ps3_read_phys_ctr - Read physical counter registers.
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| /linux-6.8/drivers/dma/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
80 depends on 440SPe || 440SP
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
154 tristate "SA-11x0 DMA support"
159 Support the DMA engine found on Intel StrongARM SA-1100 and
160 SA-1110 SoCs. This DMA engine can only be used with on-chip
220 This module can be found on Freescale Vybrid and LS-1 SoCs.
263 Enable support for the IMG multi-threaded DMA controller (MDC).
283 tristate "Intel integrated DMA 64-bit support"
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