linux/perf/arm_pmu.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/include/asm/pmu.h
20  * The ARMv7 CPU PMU supports up to 32 event counters.
25  * ARM PMU hw_event flags
40 	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
43 [0 ... C(MAX) - 1] = {							\
44 	[0 ... C(OP_MAX) - 1] = {					\
45 		[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,	\
49 /* The events for a given PMU register set. */
52 	 * The events that are active on the PMU for the given index.
80 	struct pmu	pmu;  member
84 	irqreturn_t	(*handle_irq)(struct arm_pmu *pmu);
100 	bool		secure_access; /* 32-bit ARM only */
109 	/* the attr_groups array must be NULL-terminated */
118 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
165 void kvm_host_pmu_init(struct arm_pmu *pmu);
174 void armpmu_free(struct arm_pmu *pmu);
175 int armpmu_register(struct arm_pmu *pmu);
179 #define ARMV8_PMU_PDEV_NAME "armv8-pmu"
183 #define ARMV8_SPE_PDEV_NAME "arm,spe-v1"
188 	(lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi
200 	((((attr)->cfg) >> lo) & GENMASK_ULL(hi - lo, 0))