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/qemu/hw/audio/
H A Dfmopl.c99 /* register number to channel number , slot offset */
224 static int32_t feedback2; /* connect for SLOT 2 */
286 static inline void OPL_KEYON(OPL_SLOT *SLOT) in OPL_KEYON() argument
289 SLOT->Cnt = 0; in OPL_KEYON()
291 SLOT->evm = ENV_MOD_AR; in OPL_KEYON()
292 SLOT->evs = SLOT->evsa; in OPL_KEYON()
293 SLOT->evc = EG_AST; in OPL_KEYON()
294 SLOT->eve = EG_AED; in OPL_KEYON()
297 static inline void OPL_KEYOFF(OPL_SLOT *SLOT) in OPL_KEYOFF() argument
299 if( SLOT->evm > ENV_MOD_RR) in OPL_KEYOFF()
[all …]
/qemu/hw/ufs/
H A Dtrace-events6 ufs_process_db(uint32_t slot) "UTRLDBR slot %"PRIu32""
7 ufs_process_req(uint32_t slot) "UTRLDBR slot %"PRIu32""
8 ufs_complete_req(uint32_t slot) "UTRLDBR slot %"PRIu32""
9 ufs_sendback_req(uint32_t slot) "UTRLDBR slot %"PRIu32""
10 ufs_exec_nop_cmd(uint32_t slot) "UTRLDBR slot %"PRIu32""
11 ufs_exec_scsi_cmd(uint32_t slot, uint8_t lun, uint8_t opcode) "slot %"PRIu32", lun 0x%"PRIx8", opco…
12 ufs_exec_query_cmd(uint32_t slot, uint8_t opcode) "slot %"PRIu32", opcode 0x%"PRIx8""
19 ufs_err_dma_read_utrd(uint32_t slot, uint64_t addr) "failed to read utrd. UTRLDBR slot %"PRIu32", U…
20 ufs_err_dma_read_req_upiu(uint32_t slot, uint64_t addr) "failed to read req upiu. UTRLDBR slot %"PR…
21 ufs_err_dma_read_prdt(uint32_t slot, uint64_t addr) "failed to read prdt. UTRLDBR slot %"PRIu32", p…
[all …]
/qemu/hw/acpi/
H A Dtrace-events4 mhp_acpi_invalid_slot_selected(uint32_t slot) "0x%"PRIx32
5 mhp_acpi_ejecting_invalid_slot(uint32_t slot) "0x%"PRIx32
6 mhp_acpi_read_addr_lo(uint32_t slot, uint32_t addr) "slot[0x%"PRIx32"] addr lo: 0x%"PRIx32
7 mhp_acpi_read_addr_hi(uint32_t slot, uint32_t addr) "slot[0x%"PRIx32"] addr hi: 0x%"PRIx32
8 mhp_acpi_read_size_lo(uint32_t slot, uint32_t size) "slot[0x%"PRIx32"] size lo: 0x%"PRIx32
9 mhp_acpi_read_size_hi(uint32_t slot, uint32_t size) "slot[0x%"PRIx32"] size hi: 0x%"PRIx32
10 mhp_acpi_read_pxm(uint32_t slot, uint32_t pxm) "slot[0x%"PRIx32"] proximity: 0x%"PRIx32
11 mhp_acpi_read_flags(uint32_t slot, uint32_t flags) "slot[0x%"PRIx32"] flags: 0x%"PRIx32
12 mhp_acpi_write_slot(uint32_t slot) "set active slot: 0x%"PRIx32
13 mhp_acpi_write_ost_ev(uint32_t slot, uint32_t ev) "slot[0x%"PRIx32"] OST EVENT: 0x%"PRIx32
[all …]
H A Dpcihp.c186 int slot = ctz32(slots); in acpi_pcihp_eject_slot() local
189 trace_acpi_pci_eject_slot(bsel, slot); in acpi_pcihp_eject_slot()
191 if (!bus || slot > 31) { in acpi_pcihp_eject_slot()
196 s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot); in acpi_pcihp_eject_slot()
197 s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot); in acpi_pcihp_eject_slot()
202 if (PCI_SLOT(dev->devfn) == slot) { in acpi_pcihp_eject_slot()
248 int slot = PCI_SLOT(pdev->devfn); in acpi_pcihp_update_hotplug_bus() local
251 s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot); in acpi_pcihp_update_hotplug_bus()
289 int slot = PCI_SLOT(pdev->devfn); in acpi_pcihp_device_plug_cb() local
323 s->acpi_pcihp_pci_status[bsel].up |= (1U << slot); in acpi_pcihp_device_plug_cb()
[all …]
/qemu/qapi/
H A Dacpi.json74 # @DIMM: memory slot
76 # @CPU: logical CPU slot (since 2.7)
87 # @device: device ID associated with slot
89 # @slot: slot ID, unique per slot of a given @slot-type
91 # @slot-type: type of the slot
101 'slot': 'str',
102 'slot-type': 'ACPISlotType',
117 # <- { "return": [ { "device": "d1", "slot": "0", "slot-type": "DIMM", "source": 1, "status": 0… string
118 # { "slot": "1", "slot-type": "DIMM", "source": 0, "status": 0},
119 # { "slot": "2", "slot-type": "DIMM", "source": 0, "status": 0},
[all …]
/qemu/hw/pci/
H A Dshpc.c13 /* TODO: model power only and disabled slot states. */
57 /* 4 bytes * slot # (start from 0) */
62 /* Same slot state masks are used for command and status registers */
114 /* SHPC Slot identifiers */
116 /* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
119 different chassis number values, to make chassis+physical slot unique.
121 #define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1) argument
123 #define SHPC_IDX_TO_PCI(slot) ((slot) + 1) argument
125 #define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1) argument
155 static uint8_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk) in shpc_get_status() argument
[all …]
H A Dtrace-events4 pci_pm_bad_transition(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, uint8_t old, uin…
5 pci_pm_transition(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, uint8_t old, uint8_t…
6 pci_update_mappings_del(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, int bar, uint6…
7 pci_update_mappings_add(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, int bar, uint6…
15 pci_cfg_read(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, unsigned offs, unsigned v…
16 pci_cfg_write(const char *dev, uint32_t bus, uint32_t slot, uint32_t func, unsigned offs, unsigned …
22 sriov_register_vfs(const char *name, int slot, int function, int num_vfs) "%s %02x:%x: creating %d …
23 sriov_unregister_vfs(const char *name, int slot, int function) "%s %02x:%x: Unregistering vf devs"
24 sriov_config_write(const char *name, int slot, int fun, uint32_t offset, uint32_t val, uint32_t len…
H A Dpcie_port.c48 * (chassis number, pcie physical slot number) -> pcie slot conversion
84 uint8_t slot) in pcie_chassis_find_slot_with_chassis() argument
88 if (s->slot == slot) { in pcie_chassis_find_slot_with_chassis()
95 int pcie_chassis_add_slot(struct PCIESlot *slot) in pcie_chassis_add_slot() argument
98 c = pcie_chassis_find(slot->chassis); in pcie_chassis_add_slot()
102 if (pcie_chassis_find_slot_with_chassis(c, slot->slot)) { in pcie_chassis_add_slot()
105 QLIST_INSERT_HEAD(&c->slots, slot, next); in pcie_chassis_add_slot()
208 DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
/qemu/hw/mem/
H A Dpc-dimm.c50 int slot; in pc_dimm_pre_plug() local
52 slot = object_property_get_int(OBJECT(dimm), PC_DIMM_SLOT_PROP, in pc_dimm_pre_plug()
54 if ((slot < 0 || slot >= machine->ram_slots) && in pc_dimm_pre_plug()
55 slot != PC_DIMM_UNASSIGNED_SLOT) { in pc_dimm_pre_plug()
57 "invalid slot number %d, valid range is [0-%" PRIu64 "]", in pc_dimm_pre_plug()
58 slot, machine->ram_slots - 1); in pc_dimm_pre_plug()
62 slot = pc_dimm_get_free_slot(slot == PC_DIMM_UNASSIGNED_SLOT ? NULL : &slot, in pc_dimm_pre_plug()
68 object_property_set_int(OBJECT(dimm), PC_DIMM_SLOT_PROP, slot, in pc_dimm_pre_plug()
70 trace_mhp_pc_dimm_assigned_slot(slot); in pc_dimm_pre_plug()
108 set_bit(d->slot, bitmap); in pc_dimm_slot2bitmap()
[all …]
/qemu/hw/nubus/
H A Dnubus-device.c25 qemu_set_irq(nubus->irqs[nd->slot], level); in nubus_set_irq()
38 if (nd->slot < 0 || nd->slot >= NUBUS_SLOT_NB) { in nubus_device_realize()
40 "'slot' value %d out of range (must be between 0 and %d)", in nubus_device_realize()
41 nd->slot, NUBUS_SLOT_NB - 1); in nubus_device_realize()
46 slot_offset = nd->slot * NUBUS_SUPER_SLOT_SIZE; in nubus_device_realize()
48 name = g_strdup_printf("nubus-super-slot-%x", nd->slot); in nubus_device_realize()
56 slot_offset = nd->slot * NUBUS_SLOT_SIZE; in nubus_device_realize()
58 name = g_strdup_printf("nubus-slot-%x", nd->slot); in nubus_device_realize()
87 name = g_strdup_printf("nubus-slot-%x-declaration-rom", nd->slot); in nubus_device_realize()
111 DEFINE_PROP_INT32("slot", NubusDevice, slot, -1),
H A Dnubus-bus.c129 char *ret = g_strdup_printf("%s/%s/%02x", p, bus->name, nd->slot); in nubus_get_dev_path()
133 return g_strdup_printf("%s/%02x", bus->name, nd->slot); in nubus_get_dev_path()
142 if (nd->slot == -1) { in nubus_check_address()
143 /* No slot specified, find first available free slot */ in nubus_check_address()
146 nd->slot = s; in nubus_check_address()
148 error_setg(errp, "Cannot register nubus card, no free slot " in nubus_check_address()
153 /* Slot specified, make sure the slot is available */ in nubus_check_address()
154 if (!(nubus->slot_available_mask & BIT(nd->slot))) { in nubus_check_address()
155 error_setg(errp, "Cannot register nubus card, slot %d is " in nubus_check_address()
156 "unavailable or already occupied", nd->slot); in nubus_check_address()
[all …]
/qemu/docs/specs/
H A Dacpi_pci_hotplug.rst13 PCI slot injection notification pending (IO port 0xae00-0xae03, 4-byte access)
16 Slot injection notification pending. One bit per slot.
21 PCI slot removal notification (IO port 0xae04-0xae07, 4-byte access)
24 Slot removal notification pending. One bit per slot.
33 One bit per slot.
38 - Read-only "up" register @0xae00, 4-byte access, bit per slot
39 - Read-only "down" register @0xae04, 4-byte access, bit per slot
41 write: bit per slot eject, read: hotplug feature set
42 - Read-only hotplug capable register @0xae0c, 4-byte access, bit per slot
48 bit per slot. Read-only.
H A Dacpi_erst.rst102 length, with each slot storing a single record. Not all slots need to
107 Slot 0 contains a backend storage header that identifies the contents
110 be designated to be a part of the slot 0 header. For example, at 8KiB,
111 the slot 0 header can accommodate 1021 records. Thus a storage size
112 of 8MiB (8KiB * 1024) requires an additional slot for use by the
113 header. In this scenario, slot 0 and slot 1 form the backend storage
114 header, and records can be stored starting at slot 2.
124 Slot Record
177 CPER record in the corresponding slot. Stated differently, the
179 slot index for the corresponding record in the backend storage.
[all …]
/qemu/accel/hvf/
H A Dhvf-accel-ops.c69 hvf_slot *slot; in hvf_find_overlap_slot() local
72 slot = &hvf_state->slots[x]; in hvf_find_overlap_slot()
73 if (slot->size && start < (slot->start + slot->size) && in hvf_find_overlap_slot()
74 (start + size) > slot->start) { in hvf_find_overlap_slot()
75 return slot; in hvf_find_overlap_slot()
90 static int do_hvf_set_memory(hvf_slot *slot, hv_memory_flags_t flags) in do_hvf_set_memory() argument
95 macslot = &mac_slots[slot->slot_id]; in do_hvf_set_memory()
98 if (macslot->size != slot->size) { in do_hvf_set_memory()
105 if (!slot->size) { in do_hvf_set_memory()
110 macslot->gpa_start = slot->start; in do_hvf_set_memory()
[all …]
/qemu/hw/ipack/
H A Dipack.c19 IPackDevice *ipack_device_find(IPackBus *bus, int32_t slot) in ipack_device_find() argument
26 if (ip->slot == slot) { in ipack_device_find()
49 if (idev->slot < 0) { in ipack_device_realize()
50 idev->slot = bus->free_slot; in ipack_device_realize()
52 if (idev->slot >= bus->n_slots) { in ipack_device_realize()
56 bus->free_slot = idev->slot + 1; in ipack_device_realize()
74 DEFINE_PROP_INT32("slot", IPackDevice, slot, -1),
93 VMSTATE_INT32(slot, IPackDevice),
/qemu/target/hexagon/imported/mmvec/
H A Dmacros.def243 int slot = insn->slot;
244 paddr_t pa = thread->mem_access[slot].paddr+OFFSET;
246 FLAG = (pa < (thread->mem_access[slot].paddr+LENGTH));
274 int slot = insn->slot;
277 paddr_t pa = thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMENT-1));
278 paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
292 int slot = insn->slot;
295 paddr_t pa = thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMENT-1));
296 paddr_t pa_high = thread->mem_access[slot].paddr+LEN;
309 int slot = insn->slot;
[all …]
/qemu/tests/qemu-iotests/
H A D295125 slot = None, force = False): argument
133 if slot != None:
134 crypt_options['keyslot'] = slot
163 def eraseKeyQmp(self, id, old_secret = None, slot = None, force = False): argument
169 if slot != None:
170 crypt_options['keyslot'] = slot
203 # add key to slot 1
206 # add key to slot 5
207 self.addKeyQmp("testdev", new_secret = self.secrets[2], slot=5)
209 # erase key from slot 0
[all …]
H A D14975 slot = str(i)
76 if slot in self.passwords:
77 return (self.passwords[slot], slot)
81 (pw, slot) = self.first_password()
87 slot = str(i)
88 if slot in self.passwords:
89 slots.append(slot)
129 def cryptsetup_add_password(config, slot): argument
130 """Add another password to a LUKS key slot"""
136 fh.write(config.passwords[slot])
[all …]
H A D293.out9 == adding a password to slot 4 ==
10 == adding a password to slot 1 ==
11 == adding a password to slot 3 ==
12 == adding a password to slot 2 ==
13 == erase slot 4 ==
25 == erase slot 0 and try it ==
28 == erase slot 2 and try it ==
35 == adding secret 3 (last slot) ==
37 == trying to add another slot (should fail) ==
92 == erase last secret with force by slot (should work) ==
/qemu/target/hexagon/
H A Dgenptr.h27 void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot);
28 void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
29 void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
30 void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
31 void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot);
32 void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
33 void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
34 void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
35 void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot);
H A Ddecode.c155 packet->insn[def_idx].slot; in decode_fill_newvalue_regno()
238 if (pkt->insn[i].slot == 0) { in decode_set_insn_attr_fields()
415 static SlotMask get_valid_slots(const Packet *pkt, unsigned int slot) in get_valid_slots() argument
417 if (GET_ATTRIB(pkt->insn[slot].opcode, A_EXTENSION)) { in get_valid_slots()
418 return mmvec_ext_decode_find_iclass_slots(pkt->insn[slot].opcode); in get_valid_slots()
420 return find_iclass_slots(pkt->insn[slot].opcode, in get_valid_slots()
421 pkt->insn[slot].iclass); in get_valid_slots()
546 /* We overload slot 0 for endloop. */ in has_valid_slot_assignment()
549 slot_mask = 1 << insn->slot; in has_valid_slot_assignment()
561 int slot; in decode_set_slot_number() local
[all …]
H A Dmacros.h62 * Slot 1 store with slot 0 load
63 * A slot 1 store operation with a slot 0 load operation can appear in a packet.
67 * memw(R5) = R2 // slot 1 store
68 * R3 = memh(R6) // slot 0 load
71 * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1
72 * effectively executes first, followed by the load instruction in Slot 0. If
78 * For qemu, we look for a load in slot 0 when there is a store in slot 1
86 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
97 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
101 if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
[all …]
/qemu/hw/ppc/
H A Dspapr_vhyp_mmu.c28 target_ulong slot; in h_enter() local
64 slot = ptex & 7ULL; in h_enter()
69 for (slot = 0; slot < 8; slot++) { in h_enter()
70 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { in h_enter()
75 if (slot == 8) { in h_enter()
79 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); in h_enter()
81 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); in h_enter()
87 spapr_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); in h_enter()
89 args[0] = ptex + slot; in h_enter()
410 static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) in new_hpte_load0() argument
[all …]
/qemu/crypto/
H A Dblock-luks.c426 /* Write out the partition header and key slot headers */ in qcrypto_block_luks_store_header()
692 * Given a key slot, user password, and the master key,
712 QCryptoBlockLUKSKeySlot *slot; in qcrypto_block_luks_store_key() local
723 slot = &luks->header.key_slots[slot_idx]; in qcrypto_block_luks_store_key()
724 splitkeylen = luks->header.master_key_len * slot->stripes; in qcrypto_block_luks_store_key()
726 if (qcrypto_random_bytes(slot->salt, in qcrypto_block_luks_store_key()
739 slot->salt, in qcrypto_block_luks_store_key()
765 slot->iterations = in qcrypto_block_luks_store_key()
776 slot->salt, in qcrypto_block_luks_store_key()
778 slot->iterations, in qcrypto_block_luks_store_key()
[all …]
/qemu/target/hexagon/mmvec/
H A Dsystem_ext_mmvec.c22 void mem_gather_store(CPUHexagonState *env, target_ulong vaddr, int slot) in mem_gather_store() argument
26 env->vstore_pending[slot] = 1; in mem_gather_store()
27 env->vstore[slot].va = vaddr; in mem_gather_store()
28 env->vstore[slot].size = size; in mem_gather_store()
29 memcpy(&env->vstore[slot].data.ub[0], &env->tmp_VRegs[0], size); in mem_gather_store()
32 bitmap_copy(env->vstore[slot].mask, env->vtcm_log.mask, size); in mem_gather_store()

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