62  * Slot 1 store with slot 0 load
63  * A slot 1 store operation with a slot 0 load operation can appear in a packet.
67  *         memw(R5) = R2 // slot 1 store
68  *         R3 = memh(R6) // slot 0 load
71  * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1
72  * effectively executes first, followed by the load instruction in Slot 0. If
78  * For qemu, we look for a load in slot 0 when there is  a store in slot 1
86         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
97         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
101         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
147 #define MEM_STORE1(VA, DATA, SLOT) \  argument
148     MEM_STORE1_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
155 #define MEM_STORE2(VA, DATA, SLOT) \  argument
156     MEM_STORE2_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
163 #define MEM_STORE4(VA, DATA, SLOT) \  argument
164     MEM_STORE4_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
171 #define MEM_STORE8(VA, DATA, SLOT) \  argument
172     MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
174 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)  argument
175 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)  argument
176 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)  argument
177 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)  argument
181 static inline void gen_cancel(uint32_t slot)  in gen_cancel()  argument
183     tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot);  in gen_cancel()
186 #define CANCEL gen_cancel(slot);
193 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
528         check_noshuf(env, pkt_has_store_s1, slot, EA, SIZE, GETPC()); \
552 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot)
554 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot)