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/qemu/include/hw/misc/
H A Dsifive_u_prci.h35 * Current FU540-C000 manual says ready bit is at bit 29, but
36 * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31.
/qemu/tests/tcg/s390x/
H A Dmie3-mvcrl.c37 * PoP says: Bits 32-55 of general register 0 should contain zeros; in test_bad_r0()
/qemu/bsd-user/i386/
H A Dtarget_arch_thread.h37 * SVR4/i386 ABI (pages 3-31, 3-32) says that when the program starts %edx in target_thread_init()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvzawrs.c.inc26 * The specification says:
/qemu/include/hw/ssi/
H A Dbcm2835_spi.h34 * Though BCM2835 documentation says FIFOs have a capacity of 16,
/qemu/include/hw/acpi/
H A Dich9.h36 * In ich9 spec says that pm1_cnt register is 32bit width and
/qemu/bsd-user/netbsd/
H A Dtarget_os_signal.h41 * Language spec says we must list exactly one parameter, even though we
/qemu/target/mips/
H A Dmsa.c65 * says: "When possible, this QNaN result is one of the operand QNaN in msa_reset()
H A Dfpu_helper.h75 * says: "When possible, this QNaN result is one of the operand QNaN in fp_reset()
/qemu/migration/
H A Dmultifd-zero-page.c99 * 'receivedmap' says the zero page is already received. Thus the in multifd_recv_zero_page_process()
/qemu/bsd-user/openbsd/
H A Dtarget_os_signal.h41 * Language spec says we must list exactly one parameter, even though we
/qemu/target/ppc/
H A Dmem_helper.c196 * PPC32 specification says we must generate an exception if rA is in
197 * the range of registers to be loaded. In an other hand, IBM says
335 * PowerPC specification says this is to be treated like a load in helper_icbi()
/qemu/bsd-user/freebsd/
H A Dtarget_os_signal.h50 * Language spec says we must list exactly one parameter, even though we
/qemu/docs/devel/
H A Dsubmitting-a-pull-request.rst43 request says these patches are ready to go into QEMU now, so they must
/qemu/include/system/
H A Dkvm_int.h127 * Older POSIX says that ioctl numbers are signed int, but in
/qemu/target/riscv/
H A Dtime_helper.c75 * Sstc specification says the following about timer interrupt: in riscv_timer_write_timecmp()
/qemu/target/ppc/translate/
H A Dmisc-impl.c.inc131 * ISA says that "Reserved fields in instructions are ignored
H A Dstorage-ctrl-impl.c.inc218 * ISA 3.1B says that MSR SF must be 1 when this instruction is executed;
/qemu/target/arm/tcg/
H A Dmve_helper.c35 * and 0 bits where ECI says this beat was already executed. in mve_eci_mask()
133 /* MASK01 says don't invert low half of P0 */ in mve_advance_vpt()
137 /* MASK23 says don't invert high half of P0 */ in mve_advance_vpt()
392 /* ECI says skip this beat */ \ in DO_VLDR64_SG()
416 /* ECI says skip this beat */ \
441 /* ECI says skip this beat */ \
478 /* ECI says skip this beat */ \
502 /* ECI says skip this beat */ \
525 /* ECI says skip this beat */ \
554 /* ECI says skip this beat */ \
[all …]
/qemu/target/hppa/
H A Dfpu_helper.c71 * "PA-RISC 2.0 Architecture" says it is IMPDEF whether the flushing in HELPER()
77 * TODO: "PA-RISC 2.0 Architecture" chapter 10 says that we should in HELPER()
/qemu/target/m68k/
H A Dop_helper.c577 * whereas documentation says "undefined" in HELPER()
606 * whereas documentation says "undefined" in HELPER()
696 * whereas documentation says "undefined" in HELPER()
733 * whereas documentation says "undefined" in HELPER()
/qemu/hw/cpu/
H A Darm11mpcore.c136 /* The ARM11 MPCORE TRM says the on-chip controller may have
/qemu/pc-bios/s390-ccw/
H A Dvirtio.h132 /* This bit says it's a scsi command, not an actual read or write. */
/qemu/hw/i386/
H A Dacpi-common.c43 /* ACPI spec says that LAPIC entry for non present in pc_madt_cpu_entry()
/qemu/tests/qemu-iotests/
H A D228113 # (Image header says "null-co://", actual backing file still is

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