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Searched +full:rx +full:- +full:eq (Results 1 – 9 of 9) sorted by relevance

/qemu/rust/hw/char/pl011/src/
H A Dregisters.rs3 // SPDX-License-Identifier: GPL-2.0-or-later
19 #[derive(Debug, Eq, PartialEq, qemu_api_macros::TryInto)]
40 /// `IrDA` Low-Power Counter Register
94 /// read for RX. It is a 12-bit register, where bits 7..0 are the
107 // bilge is not very const-friendly, unfortunately
142 fn default() -> Self { in default()
151 /// This has the usual inbound RS232 modem-control signals, plus flags
152 /// for RX and TX FIFO fill levels and a BUSY flag.
185 fn default() -> Self { in default()
217 /// 31:8 - Reserved, do not modify, read as zero.
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/qemu/rust/bits/src/
H A Dlib.rs1 // SPDX-License-Identifier: MIT or Apache-2.0 or GPL-2.0-or-later
70 /// type `$type`. Supported operators are `!` (unary), `-`, `&`, `^`, `|`.
101 #[derive(Clone, Copy, PartialEq, Eq)]
114 pub const fn empty() -> Self {
120 pub const fn all() -> Self {
126 pub const fn valid_bits() -> Self {
132 pub const fn valid(val: $type) -> bool {
138 pub const fn any_set(self, mask: Self) -> bool {
144 pub const fn all_set(self, mask: Self) -> bool {
150 pub const fn none_set(self, mask: Self) -> bool {
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/qemu/target/hppa/
H A Dtranslate.c22 #include "qemu/host-utils.h"
23 #include "exec/page-protection.h"
24 #include "tcg/tcg-op.h"
25 #include "tcg/tcg-op-gvec.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translation-block.h"
34 #include "exec/helper-info.c.inc"
100 #define UNALIGN(C) (C)->unalign
104 #define MMU_DISABLED(C) MMU_IDX_MMU_DISABLED((C)->mmu_idx)
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/qemu/target/m68k/
H A Dtranslate.c4 * Copyright (c) 2005-2007 CodeSourcery
23 #include "exec/translation-block.h"
25 #include "tcg/tcg-op.h"
27 #include "qemu/qemu-print.h"
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
36 #include "exec/helper-info.c.inc"
82 -offsetof(M68kCPU, env) + in m68k_tcg_init()
85 -offsetof(M68kCPU, env) + in m68k_tcg_init()
107 NULL_QREG = tcg_global_mem_new(tcg_env, -4, "NULL"); in m68k_tcg_init()
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/qemu/target/hexagon/imported/
H A Dencode_pp.def2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
26 DEF_CLASS32("---- ---- -------- PP------ --------",ALL_PP)
27 DEF_FIELD32("---- ---- -------- !!------ --------",Parse,"Packet/Loop parse bits")
28 DEF_FIELD32("!!!! ---- -------- PP------ --------",ICLASS,"Instruction Class")
57 DEF_CLASS32(ICLASS_EXTENDER" ---- -------- PP------ --------",EXTENDER)
70 DEF_CLASS32(ICLASS_V2LDST" ---- -------- PP------ --------",V2LDST)
71 DEF_CLASS32(ICLASS_V2LDST" ---1 -------- PP------ --------",V2LD)
72 DEF_CLASS32(ICLASS_V2LDST" ---0 -------- PP------ --------",V2ST)
73 DEF_CLASS32(ICLASS_V2LDST" 0--1 -------- PP------ --------",PLD)
74 DEF_CLASS32(ICLASS_V2LDST" 0--0 -------- PP------ --------",PST)
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/qemu/disas/
H A Dmips.c24 #include "disas/dis-asm.h"
73 only use ten bits). An optional two-operand form of break/sdbbp
165 but 0x8-0xf don't select bytes. */
167 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
355 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
357 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
360 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
381 "P" 5 bit performance-monitor register (OP_*_PERFREG)
386 for pretty-printing in disassembly only.
426 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
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/qemu/target/rx/
H A Ddisas.c2 * Renesas RX Disassembler
20 #include "disas/dis-asm.h"
36 uint32_t addr = ctx->addr; in decode_load_bytes()
38 g_assert(ctx->len == i); in decode_load_bytes()
39 g_assert(n <= ARRAY_SIZE(ctx->bytes)); in decode_load_bytes()
42 ctx->dis->read_memory_func(addr++, &ctx->bytes[i - 1], 1, ctx->dis); in decode_load_bytes()
43 insn |= ctx->bytes[i - 1] << (32 - i * 8); in decode_load_bytes()
45 ctx->addr = addr; in decode_load_bytes()
46 ctx->len = n; in decode_load_bytes()
53 uint32_t addr = ctx->addr; in li()
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/qemu/target/mips/tcg/
H A Dtranslate.c2 * MIPS emulation for QEMU - main translation routines
4 * Copyright (c) 2004-2005 Jocelyn Mayer
9 * Copyright (c) 2020 Philippe Mathieu-Daudé
28 #include "exec/helper-proto.h"
29 #include "exec/translation-block.h"
36 #include "exec/helper-info.c.inc"
41 * Many system-only helpers are not reachable for user-only.
153 /* PC-relative address computation / loads */
157 /* PC-relative address computation / loads */
369 /* MIPS DSP GPR-Based Shift Sub-class */
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/qemu/target/arm/tcg/
H A Dtranslate-a64.c22 #include "translate-a64.h"
74 #include "decode-sme-fa64.c.inc"
75 #include "decode-a64.c.inc"
112 ARMMMUIdx useridx = s->mmu_idx; in get_a64_user_mem_index()
114 if (unpriv && s->unpriv) { in get_a64_user_mem_index()
116 * We have pre-computed the condition for AccType_UNPRIV. in get_a64_user_mem_index()
144 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ in set_btype()
147 s->btype = -1; in set_btype()
152 if (s->btype != 0) { in reset_btype()
154 s->btype = 0; in reset_btype()
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