Lines Matching +full:rx +full:- +full:eq
2 * MIPS emulation for QEMU - main translation routines
4 * Copyright (c) 2004-2005 Jocelyn Mayer
9 * Copyright (c) 2020 Philippe Mathieu-Daudé
28 #include "exec/helper-proto.h"
29 #include "exec/translation-block.h"
36 #include "exec/helper-info.c.inc"
41 * Many system-only helpers are not reachable for user-only.
153 /* PC-relative address computation / loads */
157 /* PC-relative address computation / loads */
369 /* MIPS DSP GPR-Based Shift Sub-class */
372 /* MIPS DSP Multiply Sub-class insns */
376 /* DSP Bit/Manipulation Sub-class */
379 /* MIPS DSP Append Sub-class */
382 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
503 /* MIPS DSP Arithmetic Sub-class */
522 /* MIPS DSP Multiply Sub-class insns */
533 /* MIPS DSP Arithmetic Sub-class */
546 /* MIPS DSP Multiply Sub-class insns */
555 /* MIPS DSP Arithmetic Sub-class */
569 /* DSP Bit/Manipulation Sub-class */
579 /* MIPS DSP Arithmetic Sub-class */
587 /* DSP Compare-Pick Sub-class */
607 /* MIPS DSP GPR-Based Shift Sub-class */
634 /* MIPS DSP Multiply Sub-class insns */
661 /* DSP Bit/Manipulation Sub-class */
667 /* MIPS DSP Append Sub-class */
675 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
697 /* MIPS DSP Arithmetic Sub-class */
715 /* DSP Bit/Manipulation Sub-class */
726 /* MIPS DSP Multiply Sub-class insns */
732 /* MIPS DSP Arithmetic Sub-class */
758 /* DSP Compare-Pick Sub-class */
778 /* MIPS DSP Arithmetic Sub-class */
791 /* DSP Append Sub-class */
800 /* MIPS DSP Accumulator and DSPControl Access Sub-class */
826 /* DSP Bit/Manipulation Sub-class */
832 /* MIPS DSP Multiply Sub-class insns */
863 /* MIPS DSP GPR-Based Shift Sub-class */
1111 * +--------+----------------------------------------+
1113 * +--------+----------------------------------------+
1118 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1138 * +--------+-------------------------------+--------+
1140 * +--------+-------------------------------+--------+
1145 * -------+-------+-------+-------+-------+-------+-------+-------+-------
1171 * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[])
1280 LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags); in save_cpu_state()
1281 if (do_save_pc && ctx->base.pc_next != ctx->saved_pc) { in save_cpu_state()
1282 gen_save_pc(ctx->base.pc_next); in save_cpu_state()
1283 ctx->saved_pc = ctx->base.pc_next; in save_cpu_state()
1285 if (ctx->hflags != ctx->saved_hflags) { in save_cpu_state()
1286 tcg_gen_movi_i32(hflags, ctx->hflags); in save_cpu_state()
1287 ctx->saved_hflags = ctx->hflags; in save_cpu_state()
1288 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { in save_cpu_state()
1294 tcg_gen_movi_tl(btarget, ctx->btarget); in save_cpu_state()
1302 ctx->saved_hflags = ctx->hflags; in restore_cpu_state()
1303 switch (ctx->hflags & MIPS_HFLAG_BMASK_BASE) { in restore_cpu_state()
1309 ctx->btarget = env->btarget; in restore_cpu_state()
1319 ctx->base.is_jmp = DISAS_NORETURN; in generate_exception_err()
1350 if (ctx->hflags & MIPS_HFLAG_FRE) { in gen_load_fpr32()
1359 if (ctx->hflags & MIPS_HFLAG_FRE) { in gen_store_fpr32()
1369 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_load_fpr32h()
1378 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_store_fpr32h()
1389 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_load_fpr64()
1398 if (ctx->hflags & MIPS_HFLAG_F64) { in gen_store_fpr64()
1424 if (ctx->hflags & MIPS_HFLAG_AWRAP) { in gen_op_addr_add()
1435 if (ctx->hflags & MIPS_HFLAG_AWRAP) { in gen_op_addr_addi()
1448 if (ctx->hflags & MIPS_HFLAG_AWRAP) { in addr_add()
1455 /* Sign-extract the low 32-bits to a target_long. */
1465 /* Sign-extract the high 32-bits to a target_long. */
1477 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { in check_cp0_enabled()
1486 if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) { in check_cp1_enabled()
1498 if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) { in check_cop1x()
1504 * Verify that the processor is running with 64-bit floating-point
1509 if (unlikely(~ctx->hflags & MIPS_HFLAG_F64)) { in check_cp1_64bitmode()
1518 * even-odd pair of adjacent coprocessor general registers. When the FR bit
1527 if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) { in check_cp1_registers()
1538 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { in check_dsp()
1539 if (ctx->insn_flags & ASE_DSP) { in check_dsp()
1549 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) { in check_dsp_r2()
1550 if (ctx->insn_flags & ASE_DSP) { in check_dsp_r2()
1560 if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) { in check_dsp_r3()
1561 if (ctx->insn_flags & ASE_DSP) { in check_dsp_r3()
1575 if (unlikely(!(ctx->insn_flags & flags))) { in check_insn()
1587 if (unlikely(ctx->insn_flags & flags)) { in check_insn_opc_removed()
1609 * CPU does not support 64-bit paired-single (PS) floating point data type.
1613 if (unlikely(!ctx->ps)) { in check_ps()
1621 return ctx->hflags & MIPS_HFLAG_64; in decode_64bit_enabled()
1626 * 64-bit or 64-bit instructions are not enabled.
1638 if (unlikely(!ctx->mvh)) { in check_mvh()
1650 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) { in check_xnp()
1662 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) { in check_pw()
1674 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { in check_mt()
1688 if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { in check_cp0_mt()
1691 if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) { in check_cp0_mt()
1704 if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) { in check_nms()
1716 if (unlikely((ctx->CP0_Config5 & (1 << CP0C5_NMS)) && in check_nms_dl_il_sl_tl_l2c()
1717 !(ctx->CP0_Config1 & (1 << CP0C1_DL)) && in check_nms_dl_il_sl_tl_l2c()
1718 !(ctx->CP0_Config1 & (1 << CP0C1_IL)) && in check_nms_dl_il_sl_tl_l2c()
1719 !(ctx->CP0_Config2 & (1 << CP0C2_SL)) && in check_nms_dl_il_sl_tl_l2c()
1720 !(ctx->CP0_Config2 & (1 << CP0C2_TL)) && in check_nms_dl_il_sl_tl_l2c()
1721 !(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) { in check_nms_dl_il_sl_tl_l2c()
1732 if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) { in check_eva()
1740 * calling interface for 32 and 64-bit FPRs. No sense in changing
1930 tcg_gen_qemu_ld_tl(ret, arg1, ctx->mem_idx, memop); \
1962 target_ulong pc = ctx->base.pc_next; in pc_relative_pc()
1964 if (ctx->hflags & MIPS_HFLAG_BMASK) { in pc_relative_pc()
1965 int branch_bytes = ctx->hflags & MIPS_HFLAG_BDS16 ? 2 : 4; in pc_relative_pc()
1967 pc -= branch_bytes; in pc_relative_pc()
1978 int sizem1 = memop_size(mop) - 1; in gen_lxl()
1995 tcg_gen_shl_tl(t1, tcg_constant_tl(-1), t1); in gen_lxl()
2005 int sizem1 = size - 1; in gen_lxr()
2022 tcg_gen_xori_tl(t1, t1, size * 8 - 1); in gen_lxr()
2033 int mem_idx = ctx->mem_idx; in gen_ld()
2035 if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F | in gen_ld()
2052 ctx->default_tcg_memop_mask); in gen_ld()
2057 ctx->default_tcg_memop_mask); in gen_ld()
2095 ctx->default_tcg_memop_mask); in gen_ld()
2103 ctx->default_tcg_memop_mask); in gen_ld()
2111 ctx->default_tcg_memop_mask); in gen_ld()
2165 int mem_idx = ctx->mem_idx; in gen_st()
2173 ctx->default_tcg_memop_mask); in gen_st()
2187 ctx->default_tcg_memop_mask); in gen_st()
2194 ctx->default_tcg_memop_mask); in gen_st()
2239 eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo); in gen_st_cond()
2258 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | in gen_flt_ldst()
2259 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2267 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | in gen_flt_ldst()
2268 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2274 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_flt_ldst()
2275 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2283 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_flt_ldst()
2284 ctx->default_tcg_memop_mask); in gen_flt_ldst()
2299 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { in gen_cop1_ldst()
2425 if (rs != 0 && (ctx->insn_flags & ISA_MIPS_R6)) { in gen_logic_imm()
2956 offset = sextract32(ctx->opcode << 2, 0, 21); in gen_pcrel()
2962 offset = sextract32(ctx->opcode << 2, 0, 21); in gen_pcrel()
2964 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_pcrel()
2969 offset = sextract32(ctx->opcode << 2, 0, 21); in gen_pcrel()
2971 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_pcrel()
2978 offset = sextract32(ctx->opcode, 0, 16) << 16; in gen_pcrel()
2985 offset = sextract32(ctx->opcode, 0, 16) << 16; in gen_pcrel()
2996 offset = sextract32(ctx->opcode << 3, 0, 21); in gen_pcrel()
2998 gen_r6_ld(addr, rs, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_pcrel()
3033 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_r6_muldiv()
3049 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_r6_muldiv()
3123 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); in gen_r6_muldiv()
3124 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); in gen_r6_muldiv()
3136 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); in gen_r6_muldiv()
3137 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); in gen_r6_muldiv()
3204 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_div1_tx79()
3259 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); in gen_muldiv()
3310 tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); in gen_muldiv()
3311 tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); in gen_muldiv()
3405 * architectures are special three-operand variants with the syntax
3411 * (rd, LO, HI) <- rs * rt
3419 * (rd, LO, HI) <- (LO, HI) + rs * rt
3421 * where the low-order 32-bits of the result is placed into both the
3422 * GPR rd and the special register LO. The high-order 32-bits of the
3552 tcg_gen_subi_tl(t0, t0, TARGET_LONG_BITS - 32); in gen_cl()
3572 opc = MASK_LMMI(ctx->opcode); in gen_loongson_multimedia()
3809 tcg_gen_andi_i64(t1, t1, shift_max - 1); in gen_loongson_multimedia()
3819 * Since SRA is UndefinedResult without sign-extended inputs, in gen_loongson_multimedia()
3825 /* We want to shift in zeros for SRL; zero-extend first. */ in gen_loongson_multimedia()
3910 int cc = (ctx->opcode >> 8) & 0x7; in gen_loongson_multimedia()
3935 int lsq_rt1 = ctx->opcode & 0x1f; in gen_loongson_lswc2()
3936 int lsq_offset = sextract32(ctx->opcode, 6, 9) << 4; in gen_loongson_lswc2()
3938 int shf_offset = sextract32(ctx->opcode, 6, 8); in gen_loongson_lswc2()
3942 switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) { in gen_loongson_lswc2()
3947 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3948 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3950 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3951 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3959 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3960 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3962 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3963 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3971 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3972 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3975 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3976 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3983 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3984 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3987 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lswc2()
3988 ctx->default_tcg_memop_mask); in gen_loongson_lswc2()
3992 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { in gen_loongson_lswc2()
4000 gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_loongson_lswc2()
4011 gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_loongson_lswc2()
4021 gen_lxl(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_loongson_lswc2()
4029 gen_lxr(ctx, t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_loongson_lswc2()
4040 switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { in gen_loongson_lswc2()
4048 gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4057 gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4065 gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4072 gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); in gen_loongson_lswc2()
4092 int offset = sextract32(ctx->opcode, 3, 8); in gen_loongson_lsdc2()
4093 uint32_t opc = MASK_LOONGSON_LSDC2(ctx->opcode); in gen_loongson_lsdc2()
4097 /* Pre-conditions */ in gen_loongson_lsdc2()
4143 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB); in gen_loongson_lsdc2()
4147 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW | in gen_loongson_lsdc2()
4148 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4156 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | in gen_loongson_lsdc2()
4157 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4166 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4167 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4177 tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL | in gen_loongson_lsdc2()
4178 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4187 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4188 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4195 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); in gen_loongson_lsdc2()
4200 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UW | in gen_loongson_lsdc2()
4201 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4206 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | in gen_loongson_lsdc2()
4207 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4213 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4214 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4220 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL | in gen_loongson_lsdc2()
4221 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4227 tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ | in gen_loongson_lsdc2()
4228 ctx->default_tcg_memop_mask); in gen_loongson_lsdc2()
4334 if (ctx->base.pc_next != ctx->saved_pc) { in gen_trap()
4335 gen_save_pc(ctx->base.pc_next); in gen_trap()
4337 if (ctx->hflags != ctx->saved_hflags) { in gen_trap()
4338 tcg_gen_movi_i32(hflags, ctx->hflags); in gen_trap()
4347 if (translator_use_goto_tb(&ctx->base, dest)) { in gen_goto_tb()
4350 tcg_gen_exit_tb(ctx->base.tb, n); in gen_goto_tb()
4363 target_ulong btgt = -1; in gen_compute_branch()
4369 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_compute_branch()
4372 VADDR_PRIx "\n", ctx->base.pc_next); in gen_compute_branch()
4390 btgt = ctx->base.pc_next + insn_bytes + offset; in gen_compute_branch()
4409 btgt = ctx->base.pc_next + insn_bytes + offset; in gen_compute_branch()
4419 btgt = ctx->base.pc_next + insn_bytes + offset; in gen_compute_branch()
4425 int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000 in gen_compute_branch()
4427 btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask) in gen_compute_branch()
4433 btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) | in gen_compute_branch()
4458 case OPC_BEQ: /* rx == rx */ in gen_compute_branch()
4459 case OPC_BEQL: /* rx == rx likely */ in gen_compute_branch()
4465 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4471 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4473 case OPC_BNE: /* rx != rx */ in gen_compute_branch()
4484 btgt = ctx->base.pc_next + insn_bytes + delayslot_size; in gen_compute_branch()
4485 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4488 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 8); in gen_compute_branch()
4490 ctx->base.pc_next += 4; in gen_compute_branch()
4492 case OPC_BNEL: /* rx != rx likely */ in gen_compute_branch()
4496 ctx->base.pc_next += 4; in gen_compute_branch()
4499 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4502 ctx->hflags |= MIPS_HFLAG_BX; in gen_compute_branch()
4506 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_branch()
4509 ctx->hflags |= MIPS_HFLAG_BR; in gen_compute_branch()
4513 ctx->hflags |= MIPS_HFLAG_BR; in gen_compute_branch()
4578 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch()
4584 ctx->hflags |= MIPS_HFLAG_BL; in gen_compute_branch()
4593 ctx->btarget = btgt; in gen_compute_branch()
4597 ctx->hflags |= MIPS_HFLAG_BDS16; in gen_compute_branch()
4600 ctx->hflags |= MIPS_HFLAG_BDS32; in gen_compute_branch()
4606 int lowbit = !!(ctx->hflags & MIPS_HFLAG_M16); in gen_compute_branch()
4609 ctx->base.pc_next + post_delay + lowbit); in gen_compute_branch()
4614 ctx->hflags |= MIPS_HFLAG_B16; in gen_compute_branch()
4637 * so this is a simple sign-extension. in gen_bitops()
4662 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); in gen_bitops()
4677 tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); in gen_bitops()
4790 tcg_gen_shri_i64(t2, t2, 32 - bits); in gen_align_bits()
4797 tcg_gen_shri_tl(t1, t1, 64 - bits); in gen_align_bits()
4918 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mfhc0()
4929 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mfhc0()
4941 ctx->CP0_LLAddr_shift); in gen_mfhc0()
4945 CP0_CHECK(ctx->mrp); in gen_mfhc0()
4964 CP0_CHECK(ctx->mi); in gen_mfhc0()
5000 uint64_t mask = ctx->PAMask >> 36; in gen_mthc0()
5006 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mthc0()
5018 CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA); in gen_mthc0()
5031 * LLAddr is read-only (the only exception is bit 0 if LLB is in gen_mthc0()
5039 CP0_CHECK(ctx->mrp); in gen_mthc0()
5058 CP0_CHECK(ctx->mi); in gen_mthc0()
5093 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_mfc0_unimplemented()
5131 CP0_CHECK(ctx->vp); in gen_mfc0()
5142 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_mfc0()
5193 if (ctx->rxi) { in gen_mfc0()
5250 if (ctx->rxi) { in gen_mfc0()
5261 CP0_CHECK(ctx->vp); in gen_mfc0()
5282 CP0_CHECK(ctx->ulri); in gen_mfc0()
5289 CP0_CHECK(ctx->mi); in gen_mfc0()
5309 CP0_CHECK(ctx->sc); in gen_mfc0()
5315 CP0_CHECK(ctx->sc); in gen_mfc0()
5321 CP0_CHECK(ctx->sc); in gen_mfc0()
5404 CP0_CHECK(ctx->bi); in gen_mfc0()
5409 CP0_CHECK(ctx->bp); in gen_mfc0()
5414 CP0_CHECK(ctx->bi); in gen_mfc0()
5427 translator_io_start(&ctx->base); in gen_mfc0()
5435 gen_save_pc(ctx->base.pc_next + 4); in gen_mfc0()
5436 ctx->base.is_jmp = DISAS_EXIT; in gen_mfc0()
5525 CP0_CHECK(ctx->cmgcr); in gen_mfc0()
5580 CP0_CHECK(ctx->mrp); in gen_mfc0()
5585 CP0_CHECK(ctx->mrp); in gen_mfc0()
5603 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
5621 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mfc0()
5645 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_mfc0()
5832 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_mfc0()
5834 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_mfc0()
5863 icount = translator_io_start(&ctx->base); in gen_mtc0()
5888 CP0_CHECK(ctx->vp); in gen_mtc0()
5995 CP0_CHECK(ctx->vp); in gen_mtc0()
6015 CP0_CHECK(ctx->ulri); in gen_mtc0()
6021 CP0_CHECK(ctx->mi); in gen_mtc0()
6039 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6042 CP0_CHECK(ctx->sc); in gen_mtc0()
6047 CP0_CHECK(ctx->sc); in gen_mtc0()
6052 CP0_CHECK(ctx->sc); in gen_mtc0()
6120 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6186 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6187 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6194 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6201 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6208 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6225 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6226 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6264 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6274 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6280 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6285 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6291 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6314 CP0_CHECK(ctx->mrp); in gen_mtc0()
6319 CP0_CHECK(ctx->mrp); in gen_mtc0()
6337 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
6355 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_mtc0()
6378 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_mtc0()
6397 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6398 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6406 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6413 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6417 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6422 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6428 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6435 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6495 ctx->base.is_jmp = DISAS_STOP; in gen_mtc0()
6576 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_mtc0()
6578 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_mtc0()
6596 gen_save_pc(ctx->base.pc_next + 4); in gen_mtc0()
6597 ctx->base.is_jmp = DISAS_EXIT; in gen_mtc0()
6638 CP0_CHECK(ctx->vp); in gen_dmfc0()
6649 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_dmfc0()
6748 CP0_CHECK(ctx->vp); in gen_dmfc0()
6768 CP0_CHECK(ctx->ulri); in gen_dmfc0()
6774 CP0_CHECK(ctx->mi); in gen_dmfc0()
6794 CP0_CHECK(ctx->sc); in gen_dmfc0()
6799 CP0_CHECK(ctx->sc); in gen_dmfc0()
6804 CP0_CHECK(ctx->sc); in gen_dmfc0()
6885 CP0_CHECK(ctx->bi); in gen_dmfc0()
6890 CP0_CHECK(ctx->bp); in gen_dmfc0()
6895 CP0_CHECK(ctx->bi); in gen_dmfc0()
6908 translator_io_start(&ctx->base); in gen_dmfc0()
6915 gen_save_pc(ctx->base.pc_next + 4); in gen_dmfc0()
6916 ctx->base.is_jmp = DISAS_EXIT; in gen_dmfc0()
7002 CP0_CHECK(ctx->cmgcr); in gen_dmfc0()
7056 CP0_CHECK(ctx->mrp); in gen_dmfc0()
7061 CP0_CHECK(ctx->mrp); in gen_dmfc0()
7079 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
7097 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmfc0()
7118 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_dmfc0()
7300 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_dmfc0()
7302 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_dmfc0()
7330 icount = translator_io_start(&ctx->base); in gen_dmtc0()
7355 CP0_CHECK(ctx->vp); in gen_dmtc0()
7462 CP0_CHECK(ctx->vp); in gen_dmtc0()
7482 CP0_CHECK(ctx->ulri); in gen_dmtc0()
7488 CP0_CHECK(ctx->mi); in gen_dmtc0()
7508 CP0_CHECK(ctx->sc); in gen_dmtc0()
7513 CP0_CHECK(ctx->sc); in gen_dmtc0()
7518 CP0_CHECK(ctx->sc); in gen_dmtc0()
7586 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7625 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7648 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7656 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
7657 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
7664 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7671 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7678 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7695 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
7696 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
7734 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7744 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7750 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7760 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7775 CP0_CHECK(ctx->mrp); in gen_dmtc0()
7780 CP0_CHECK(ctx->mrp); in gen_dmtc0()
7798 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmtc0()
7816 CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); in gen_dmtc0()
7837 CP0_CHECK(!(ctx->insn_flags & ISA_MIPS_R6)); in gen_dmtc0()
7856 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
7857 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
7864 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7871 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7878 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7885 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7892 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
7952 ctx->base.is_jmp = DISAS_STOP; in gen_dmtc0()
8033 CP0_CHECK(ctx->kscrexist & (1 << sel)); in gen_dmtc0()
8035 offsetof(CPUMIPSState, CP0_KScratch[sel - 2])); in gen_dmtc0()
8053 gen_save_pc(ctx->base.pc_next + 4); in gen_dmtc0()
8054 ctx->base.is_jmp = DISAS_EXIT; in gen_dmtc0()
8067 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in gen_mftr()
8070 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && in gen_mftr()
8071 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != in gen_mftr()
8072 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { in gen_mftr()
8073 tcg_gen_movi_tl(t0, -1); in gen_mftr()
8074 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > in gen_mftr()
8075 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { in gen_mftr()
8076 tcg_gen_movi_tl(t0, -1); in gen_mftr()
8291 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); in gen_mttr()
8295 if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && in gen_mttr()
8296 ((env->tcs[other_tc].CP0_TCBind & (0xf << CP0TCBd_CurVPE)) != in gen_mttr()
8297 (env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE)))) { in gen_mttr()
8300 } else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > in gen_mttr()
8301 (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) { in gen_mttr()
8471 ctx->base.is_jmp = DISAS_STOP; in gen_mttr()
8501 gen_mfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); in gen_cp0()
8509 gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); in gen_cp0()
8520 gen_dmfc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); in gen_cp0()
8529 gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); in gen_cp0()
8540 gen_mfhc0(ctx, cpu_gpr[rt], rd, ctx->opcode & 0x7); in gen_cp0()
8548 gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7); in gen_cp0()
8558 gen_mftr(env, ctx, rt, rd, (ctx->opcode >> 5) & 1, in gen_cp0()
8559 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); in gen_cp0()
8564 gen_mttr(env, ctx, rd, rt, (ctx->opcode >> 5) & 1, in gen_cp0()
8565 ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); in gen_cp0()
8570 if (!env->tlb->helper_tlbwi) { in gen_cp0()
8577 if (ctx->ie >= 2) { in gen_cp0()
8578 if (!env->tlb->helper_tlbinv) { in gen_cp0()
8586 if (ctx->ie >= 2) { in gen_cp0()
8587 if (!env->tlb->helper_tlbinvf) { in gen_cp0()
8595 if (!env->tlb->helper_tlbwr) { in gen_cp0()
8602 if (!env->tlb->helper_tlbp) { in gen_cp0()
8609 if (!env->tlb->helper_tlbr) { in gen_cp0()
8615 if ((ctx->insn_flags & ISA_MIPS_R6) && in gen_cp0()
8616 (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_cp0()
8619 int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6; in gen_cp0()
8620 if (ctx->opcode & (1 << bit_shift)) { in gen_cp0()
8631 ctx->base.is_jmp = DISAS_EXIT; in gen_cp0()
8637 if ((ctx->insn_flags & ISA_MIPS_R6) && in gen_cp0()
8638 (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_cp0()
8641 if (!(ctx->hflags & MIPS_HFLAG_DM)) { in gen_cp0()
8646 ctx->base.is_jmp = DISAS_EXIT; in gen_cp0()
8652 if ((ctx->insn_flags & ISA_MIPS_R6) && in gen_cp0()
8653 (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_cp0()
8657 ctx->base.pc_next += 4; in gen_cp0()
8659 ctx->base.pc_next -= 4; in gen_cp0()
8661 ctx->base.is_jmp = DISAS_NORETURN; in gen_cp0()
8680 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_compute_branch1()
8689 btarget = ctx->base.pc_next + 4 + offset; in gen_compute_branch1()
8714 ctx->hflags |= MIPS_HFLAG_BL; in gen_compute_branch1()
8764 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch1()
8771 ctx->btarget = btarget; in gen_compute_branch1()
8772 ctx->hflags |= MIPS_HFLAG_BDS32; in gen_compute_branch1()
8783 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_compute_branch1_r6()
8786 VADDR_PRIx "\n", ctx->base.pc_next); in gen_compute_branch1_r6()
8795 btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_branch1_r6()
8800 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch1_r6()
8804 ctx->hflags |= MIPS_HFLAG_BC; in gen_compute_branch1_r6()
8814 ctx->btarget = btarget; in gen_compute_branch1_r6()
8818 ctx->hflags |= MIPS_HFLAG_BDS16; in gen_compute_branch1_r6()
8821 ctx->hflags |= MIPS_HFLAG_BDS32; in gen_compute_branch1_r6()
9072 ctx->base.is_jmp = DISAS_STOP; in gen_cp1()
9272 uint32_t func = ctx->opcode & 0x3f; in gen_farith()
9332 if (ctx->abs2008) { in gen_farith()
9353 if (ctx->abs2008) { in gen_farith()
9368 if (ctx->nan2008) { in gen_farith()
9383 if (ctx->nan2008) { in gen_farith()
9398 if (ctx->nan2008) { in gen_farith()
9413 if (ctx->nan2008) { in gen_farith()
9426 if (ctx->nan2008) { in gen_farith()
9439 if (ctx->nan2008) { in gen_farith()
9452 if (ctx->nan2008) { in gen_farith()
9465 if (ctx->nan2008) { in gen_farith()
9582 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9606 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9628 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9649 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
9687 if (ctx->nan2008) { in gen_farith()
9702 if (ctx->nan2008) { in gen_farith()
9740 if (ctx->opcode & (1 << 6)) { in gen_farith()
9741 gen_cmpabs_s(ctx, func - 48, ft, fs, cc); in gen_farith()
9743 gen_cmp_s(ctx, func - 48, ft, fs, cc); in gen_farith()
9810 if (ctx->abs2008) { in gen_farith()
9833 if (ctx->abs2008) { in gen_farith()
9847 if (ctx->nan2008) { in gen_farith()
9861 if (ctx->nan2008) { in gen_farith()
9875 if (ctx->nan2008) { in gen_farith()
9889 if (ctx->nan2008) { in gen_farith()
9904 if (ctx->nan2008) { in gen_farith()
9919 if (ctx->nan2008) { in gen_farith()
9934 if (ctx->nan2008) { in gen_farith()
9949 if (ctx->nan2008) { in gen_farith()
10068 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10091 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10112 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10133 if (ctx->insn_flags & ISA_MIPS_R6) { in gen_farith()
10172 if (ctx->opcode & (1 << 6)) { in gen_farith()
10173 gen_cmpabs_d(ctx, func - 48, ft, fs, cc); in gen_farith()
10175 gen_cmp_d(ctx, func - 48, ft, fs, cc); in gen_farith()
10196 if (ctx->nan2008) { in gen_farith()
10210 if (ctx->nan2008) { in gen_farith()
10530 if (ctx->opcode & (1 << 6)) { in gen_farith()
10531 gen_cmpabs_ps(ctx, func - 48, ft, fs, cc); in gen_farith()
10533 gen_cmp_ps(ctx, func - 48, ft, fs, cc); in gen_farith()
10566 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_flt3_ldst()
10576 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10586 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10595 tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UL); in gen_flt3_ldst()
10604 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10613 tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_flt3_ldst()
10859 translator_io_start(&ctx->base); in gen_rdhwr()
10867 gen_save_pc(ctx->base.pc_next + 4); in gen_rdhwr()
10868 ctx->base.is_jmp = DISAS_EXIT; in gen_rdhwr()
10898 if ((ctx->hflags & MIPS_HFLAG_CP0) || in gen_rdhwr()
10899 (ctx->hflags & MIPS_HFLAG_HWRENA_ULR)) { in gen_rdhwr()
10917 ctx->hflags &= ~MIPS_HFLAG_BMASK; in clear_branch_hflags()
10918 if (ctx->base.is_jmp == DISAS_NEXT) { in clear_branch_hflags()
10922 * It is not safe to save ctx->hflags as hflags may be changed in clear_branch_hflags()
10931 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_branch()
10932 int proc_hflags = ctx->hflags & MIPS_HFLAG_BMASK; in gen_branch()
10935 ctx->base.is_jmp = DISAS_NORETURN; in gen_branch()
10938 gen_goto_tb(ctx, 0, ctx->base.pc_next + insn_bytes); in gen_branch()
10945 gen_goto_tb(ctx, 0, ctx->btarget); in gen_branch()
10949 gen_goto_tb(ctx, 0, ctx->btarget); in gen_branch()
10957 gen_goto_tb(ctx, 1, ctx->base.pc_next + insn_bytes); in gen_branch()
10959 gen_goto_tb(ctx, 0, ctx->btarget); in gen_branch()
10964 if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { in gen_branch()
10994 int m16_lowbit = (ctx->hflags & MIPS_HFLAG_M16) != 0; in gen_compute_compact_branch()
10996 if (ctx->hflags & MIPS_HFLAG_BMASK) { in gen_compute_compact_branch()
10999 VADDR_PRIx "\n", ctx->base.pc_next); in gen_compute_compact_branch()
11013 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11016 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11024 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11031 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11036 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11040 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11048 ctx->btarget = addr_add(ctx, ctx->base.pc_next + 4, offset); in gen_compute_compact_branch()
11067 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11070 ctx->hflags |= MIPS_HFLAG_BR; in gen_compute_compact_branch()
11073 tcg_gen_movi_tl(cpu_gpr[31], ctx->base.pc_next + 4 + m16_lowbit); in gen_compute_compact_branch()
11076 ctx->hflags |= MIPS_HFLAG_B; in gen_compute_compact_branch()
11204 gen_goto_tb(ctx, 1, ctx->btarget); in gen_compute_compact_branch()
11207 ctx->hflags |= MIPS_HFLAG_FBNSLOT; in gen_compute_compact_branch()
11211 void gen_addiupc(DisasContext *ctx, int rx, int imm, in gen_addiupc() argument
11216 if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { in gen_addiupc()
11225 tcg_gen_movi_tl(cpu_gpr[rx], npc); in gen_addiupc()
11242 bool is_user = (ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM; in is_uhi()
11260 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_ldxs()
11300 * Values for microMIPS fmt field. Variable-width, depending on which
11332 if (!(ctx->insn_flags & INSN_OCTEON)) { in gen_mips_lx()
11347 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB); in gen_mips_lx()
11351 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SW); in gen_mips_lx()
11355 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_SL); in gen_mips_lx()
11360 tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in gen_mips_lx()
11832 op2 = MASK_SHLL_QB(ctx->opcode); in gen_mipsdsp_shift()
11931 op2 = MASK_SHLL_OB(ctx->opcode); in gen_mipsdsp_shift()
12376 imm = (ctx->opcode >> 16) & 0xFF; in gen_mipsdsp_bitinsn()
12397 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_bitinsn()
12421 imm = (ctx->opcode >> 16) & 0xFF; in gen_mipsdsp_bitinsn()
12433 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_bitinsn()
12445 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_bitinsn()
12684 switch (MASK_APPEND(ctx->opcode)) { in gen_mipsdsp_append()
12687 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 32 - sa); in gen_mipsdsp_append()
12695 tcg_gen_shli_tl(t0, t0, 32 - sa); in gen_mipsdsp_append()
12705 tcg_gen_shri_tl(t0, t0, 8 * (4 - sa)); in gen_mipsdsp_append()
12718 switch (MASK_DAPPEND(ctx->opcode)) { in gen_mipsdsp_append()
12721 tcg_gen_deposit_tl(cpu_gpr[rt], t0, cpu_gpr[rt], sa, 64 - sa); in gen_mipsdsp_append()
12726 tcg_gen_shli_tl(t0, t0, 64 - (0x20 | sa)); in gen_mipsdsp_append()
12732 tcg_gen_shli_tl(t0, t0, 64 - sa); in gen_mipsdsp_append()
12740 tcg_gen_shri_tl(t0, t0, 8 * (8 - sa)); in gen_mipsdsp_append()
12833 imm = (ctx->opcode >> 20) & 0x3F; in gen_mipsdsp_accinsn()
12847 imm = (ctx->opcode >> 11) & 0x3FF; in gen_mipsdsp_accinsn()
12852 imm = (ctx->opcode >> 16) & 0x03FF; in gen_mipsdsp_accinsn()
12868 int shift = (ctx->opcode >> 19) & 0x7F; in gen_mipsdsp_accinsn()
12869 int ac = (ctx->opcode >> 11) & 0x03; in gen_mipsdsp_accinsn()
12877 int ac = (ctx->opcode >> 11) & 0x03; in gen_mipsdsp_accinsn()
12977 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special_r6()
12978 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special_r6()
12979 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special_r6()
12980 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special_r6()
12982 op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special_r6()
12988 op2 = MASK_R6_MULDIV(ctx->opcode); in decode_opc_special_r6()
13023 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { in decode_opc_special_r6()
13024 ctx->base.is_jmp = DISAS_SEMIHOST; in decode_opc_special_r6()
13026 if (ctx->hflags & MIPS_HFLAG_SBRI) { in decode_opc_special_r6()
13052 op2 = MASK_R6_MULDIV(ctx->opcode); in decode_opc_special_r6()
13081 int rs = extract32(ctx->opcode, 21, 5); in decode_opc_special_tx79()
13082 int rt = extract32(ctx->opcode, 16, 5); in decode_opc_special_tx79()
13083 int rd = extract32(ctx->opcode, 11, 5); in decode_opc_special_tx79()
13084 uint32_t op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special_tx79()
13131 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special_legacy()
13132 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special_legacy()
13133 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special_legacy()
13135 op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special_legacy()
13153 if (env->CP0_Config1 & (1 << CP0C1_FP)) { in decode_opc_special_legacy()
13155 gen_movci(ctx, rd, rs, (ctx->opcode >> 18) & 0x7, in decode_opc_special_legacy()
13156 (ctx->opcode >> 16) & 1); in decode_opc_special_legacy()
13204 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special()
13205 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special()
13206 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special()
13207 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special()
13209 op1 = MASK_SPECIAL(ctx->opcode); in decode_opc_special()
13214 if ((ctx->insn_flags & ISA_MIPS_R6) && in decode_opc_special()
13215 (ctx->hflags & MIPS_HFLAG_BMASK)) { in decode_opc_special()
13225 switch ((ctx->opcode >> 21) & 0x1f) { in decode_opc_special()
13227 /* rotr is decoded as srl on non-R2 CPUs */ in decode_opc_special()
13228 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13251 switch ((ctx->opcode >> 6) & 0x1f) { in decode_opc_special()
13253 /* rotrv is decoded as srlv on non-R2 CPUs */ in decode_opc_special()
13254 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13286 gen_trap(ctx, op1, rs, rt, -1, extract32(ctx->opcode, 6, 10)); in decode_opc_special()
13301 generate_exception_break(ctx, extract32(ctx->opcode, 6, 20)); in decode_opc_special()
13305 gen_sync(extract32(ctx->opcode, 6, 5)); in decode_opc_special()
13319 switch ((ctx->opcode >> 21) & 0x1f) { in decode_opc_special()
13321 /* drotr is decoded as dsrl on non-R2 CPUs */ in decode_opc_special()
13322 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13337 switch ((ctx->opcode >> 21) & 0x1f) { in decode_opc_special()
13339 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ in decode_opc_special()
13340 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13369 switch ((ctx->opcode >> 6) & 0x1f) { in decode_opc_special()
13371 /* drotrv is decoded as dsrlv on non-R2 CPUs */ in decode_opc_special()
13372 if (ctx->insn_flags & ISA_MIPS_R2) { in decode_opc_special()
13388 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_special()
13390 } else if (ctx->insn_flags & INSN_R5900) { in decode_opc_special()
13404 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special2_legacy()
13405 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special2_legacy()
13406 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special2_legacy()
13408 op1 = MASK_SPECIAL2(ctx->opcode); in decode_opc_special2_legacy()
13426 if (is_uhi(ctx, extract32(ctx->opcode, 6, 20))) { in decode_opc_special2_legacy()
13427 ctx->base.is_jmp = DISAS_SEMIHOST; in decode_opc_special2_legacy()
13458 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special3_r6()
13459 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special3_r6()
13460 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special3_r6()
13461 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special3_r6()
13462 imm = (int16_t)ctx->opcode >> 7; in decode_opc_special3_r6()
13464 op1 = MASK_SPECIAL3(ctx->opcode); in decode_opc_special3_r6()
13468 /* hint codes 24-31 are reserved and signal RI */ in decode_opc_special3_r6()
13475 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { in decode_opc_special3_r6()
13491 op2 = MASK_BSHFL(ctx->opcode); in decode_opc_special3_r6()
13507 if (unlikely(ctx->gi <= 1)) { in decode_opc_special3_r6()
13511 switch ((ctx->opcode >> 6) & 3) { in decode_opc_special3_r6()
13516 gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2)); in decode_opc_special3_r6()
13538 op2 = MASK_DBSHFL(ctx->opcode); in decode_opc_special3_r6()
13570 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special3_legacy()
13571 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special3_legacy()
13572 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special3_legacy()
13574 op1 = MASK_SPECIAL3(ctx->opcode); in decode_opc_special3_legacy()
13581 if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MUL_PH_DSP)) { in decode_opc_special3_legacy()
13582 op2 = MASK_ADDUH_QB(ctx->opcode); in decode_opc_special3_legacy()
13614 op2 = MASK_LX(ctx->opcode); in decode_opc_special3_legacy()
13631 op2 = MASK_ABSQ_S_PH(ctx->opcode); in decode_opc_special3_legacy()
13662 op2 = MASK_ADDU_QB(ctx->opcode); in decode_opc_special3_legacy()
13700 op2 = MASK_CMPU_EQ_QB(ctx->opcode); in decode_opc_special3_legacy()
13733 MIPS_INVAL("MASK CMPU.EQ.QB"); in decode_opc_special3_legacy()
13742 op2 = MASK_DPA_W_PH(ctx->opcode); in decode_opc_special3_legacy()
13775 op2 = MASK_INSV(ctx->opcode); in decode_opc_special3_legacy()
13805 op2 = MASK_EXTR_W(ctx->opcode); in decode_opc_special3_legacy()
13838 op2 = MASK_ABSQ_S_QH(ctx->opcode); in decode_opc_special3_legacy()
13874 op2 = MASK_ADDU_OB(ctx->opcode); in decode_opc_special3_legacy()
13913 op2 = MASK_CMPU_EQ_OB(ctx->opcode); in decode_opc_special3_legacy()
13961 op2 = MASK_DEXTR_W(ctx->opcode); in decode_opc_special3_legacy()
13995 op2 = MASK_DPAQ_W_QH(ctx->opcode); in decode_opc_special3_legacy()
14034 op2 = MASK_INSV(ctx->opcode); in decode_opc_special3_legacy()
14077 uint32_t opc = MASK_MMI(ctx->opcode); in decode_mmi()
14078 int rs = extract32(ctx->opcode, 21, 5); in decode_mmi()
14079 int rt = extract32(ctx->opcode, 16, 5); in decode_mmi()
14080 int rd = extract32(ctx->opcode, 11, 5); in decode_mmi()
14108 * The TX79-specific instruction Store Quadword
14110 * +--------+-------+-------+------------------------+
14112 * +--------+-------+-------+------------------------+
14117 * +--------+-------+-------+-------+-------+--------+
14119 * +--------+-------+-------+-------+-------+--------+
14130 int base = extract32(ctx->opcode, 21, 5); in decode_mmi_sq()
14131 int rt = extract32(ctx->opcode, 16, 5); in decode_mmi_sq()
14132 int offset = extract32(ctx->opcode, 0, 16); in decode_mmi_sq()
14135 uint32_t op1 = MASK_SPECIAL3(ctx->opcode); in decode_mmi_sq()
14136 uint32_t op2 = extract32(ctx->opcode, 6, 5); in decode_mmi_sq()
14139 int rd = extract32(ctx->opcode, 11, 5); in decode_mmi_sq()
14157 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_special3()
14158 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_special3()
14159 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_special3()
14160 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_special3()
14161 imm = sextract32(ctx->opcode, 7, 9); in decode_opc_special3()
14163 op1 = MASK_SPECIAL3(ctx->opcode); in decode_opc_special3()
14170 if (ctx->eva) { in decode_opc_special3()
14198 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { in decode_opc_special3()
14216 op2 = MASK_BSHFL(ctx->opcode); in decode_opc_special3()
14244 op2 = MASK_DBSHFL(ctx->opcode); in decode_opc_special3()
14261 op2 = MASK_DBSHFL(ctx->opcode); in decode_opc_special3()
14268 gen_rdhwr(ctx, rt, rd, extract32(ctx->opcode, 6, 3)); in decode_opc_special3()
14292 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_special3()
14307 op = MASK_OP_MAJOR(ctx->opcode); in decode_opc_legacy()
14308 rs = (ctx->opcode >> 21) & 0x1f; in decode_opc_legacy()
14309 rt = (ctx->opcode >> 16) & 0x1f; in decode_opc_legacy()
14310 rd = (ctx->opcode >> 11) & 0x1f; in decode_opc_legacy()
14311 sa = (ctx->opcode >> 6) & 0x1f; in decode_opc_legacy()
14312 imm = (int16_t)ctx->opcode; in decode_opc_legacy()
14319 if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) { in decode_opc_legacy()
14324 if (TARGET_LONG_BITS == 32 && (ctx->insn_flags & ASE_MXU)) { in decode_opc_legacy()
14325 if (decode_ase_mxu(ctx, ctx->opcode)) { in decode_opc_legacy()
14333 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14343 op1 = MASK_REGIMM(ctx->opcode); in decode_opc_legacy()
14354 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); in decode_opc_legacy()
14358 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14361 gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); in decode_opc_legacy()
14366 gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); in decode_opc_legacy()
14377 gen_trap(ctx, op1, rs, -1, imm, 0); in decode_opc_legacy()
14389 ctx->base.is_jmp = DISAS_STOP; in decode_opc_legacy()
14396 gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2, 4); in decode_opc_legacy()
14422 op1 = MASK_CP0(ctx->opcode); in decode_opc_legacy()
14455 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); in decode_opc_legacy()
14464 op2 = MASK_MFMC0(ctx->opcode); in decode_opc_legacy()
14488 if (ctx->vp) { in decode_opc_legacy()
14495 if (ctx->vp) { in decode_opc_legacy()
14509 ctx->base.is_jmp = DISAS_STOP; in decode_opc_legacy()
14520 gen_save_pc(ctx->base.pc_next + 4); in decode_opc_legacy()
14521 ctx->base.is_jmp = DISAS_EXIT; in decode_opc_legacy()
14546 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14570 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; in decode_opc_legacy()
14575 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14588 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14631 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14654 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14662 if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { in decode_opc_legacy()
14681 op1 = MASK_CP1(ctx->opcode); in decode_opc_legacy()
14707 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14709 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), in decode_opc_legacy()
14717 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), in decode_opc_legacy()
14724 gen_compute_branch1_r6(ctx, MASK_CP1(ctx->opcode), in decode_opc_legacy()
14738 gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), in decode_opc_legacy()
14747 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, in decode_opc_legacy()
14753 int r6_op = ctx->opcode & FOP(0x3f, 0x1f); in decode_opc_legacy()
14755 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14779 gen_r6_cmp_s(ctx, ctx->opcode & 0x1f, rt, rd, sa); in decode_opc_legacy()
14803 gen_r6_cmp_d(ctx, ctx->opcode & 0x1f, rt, rd, sa); in decode_opc_legacy()
14806 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), in decode_opc_legacy()
14812 gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa, in decode_opc_legacy()
14824 /* Compact branches [R6] and COP2 [non-R6] */ in decode_opc_legacy()
14827 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14830 sextract32(ctx->opcode << 2, 0, 28)); in decode_opc_legacy()
14831 } else if (ctx->insn_flags & ASE_LEXT) { in decode_opc_legacy()
14841 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14845 sextract32(ctx->opcode << 2, 0, 23)); in decode_opc_legacy()
14850 } else if (ctx->insn_flags & ASE_LEXT) { in decode_opc_legacy()
14865 if (ctx->CP0_Config1 & (1 << CP0C1_FP)) { in decode_opc_legacy()
14867 op1 = MASK_CP3(ctx->opcode); in decode_opc_legacy()
14915 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14936 if (ctx->insn_flags & INSN_R5900) { in decode_opc_legacy()
14943 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14960 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14969 if (ctx->insn_flags & ISA_MIPS_R6) { in decode_opc_legacy()
14987 offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; in decode_opc_legacy()
14996 gen_pcrel(ctx, ctx->opcode, ctx->base.pc_next, rs); in decode_opc_legacy()
15008 if (ctx->base.pc_next & 0x3) { in decode_opc()
15009 env->CP0_BadVAddr = ctx->base.pc_next; in decode_opc()
15015 if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) { in decode_opc()
15019 tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); in decode_opc()
15020 gen_goto_tb(ctx, 1, ctx->base.pc_next + 4); in decode_opc()
15024 /* Transition to the auto-generated decoder. */ in decode_opc()
15027 if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { in decode_opc()
15030 if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { in decode_opc()
15033 if (TARGET_LONG_BITS == 64 && decode_ext_loongson(ctx, ctx->opcode)) { in decode_opc()
15037 if (ase_lcsr_available(env) && decode_ase_lcsr(ctx, ctx->opcode)) { in decode_opc()
15040 if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) { in decode_opc()
15046 if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { in decode_opc()
15051 if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) { in decode_opc()
15067 ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK; in mips_tr_init_disas_context()
15068 ctx->saved_pc = -1; in mips_tr_init_disas_context()
15069 ctx->insn_flags = env->insn_flags; in mips_tr_init_disas_context()
15070 ctx->CP0_Config0 = env->CP0_Config0; in mips_tr_init_disas_context()
15071 ctx->CP0_Config1 = env->CP0_Config1; in mips_tr_init_disas_context()
15072 ctx->CP0_Config2 = env->CP0_Config2; in mips_tr_init_disas_context()
15073 ctx->CP0_Config3 = env->CP0_Config3; in mips_tr_init_disas_context()
15074 ctx->CP0_Config5 = env->CP0_Config5; in mips_tr_init_disas_context()
15075 ctx->btarget = 0; in mips_tr_init_disas_context()
15076 ctx->kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; in mips_tr_init_disas_context()
15077 ctx->rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; in mips_tr_init_disas_context()
15078 ctx->ie = (env->CP0_Config4 >> CP0C4_IE) & 3; in mips_tr_init_disas_context()
15079 ctx->bi = (env->CP0_Config3 >> CP0C3_BI) & 1; in mips_tr_init_disas_context()
15080 ctx->bp = (env->CP0_Config3 >> CP0C3_BP) & 1; in mips_tr_init_disas_context()
15081 ctx->PAMask = env->PAMask; in mips_tr_init_disas_context()
15082 ctx->mvh = (env->CP0_Config5 >> CP0C5_MVH) & 1; in mips_tr_init_disas_context()
15083 ctx->eva = (env->CP0_Config5 >> CP0C5_EVA) & 1; in mips_tr_init_disas_context()
15084 ctx->sc = (env->CP0_Config3 >> CP0C3_SC) & 1; in mips_tr_init_disas_context()
15085 ctx->CP0_LLAddr_shift = env->CP0_LLAddr_shift; in mips_tr_init_disas_context()
15086 ctx->cmgcr = (env->CP0_Config3 >> CP0C3_CMGCR) & 1; in mips_tr_init_disas_context()
15088 ctx->hflags = (uint32_t)ctx->base.tb->flags; /* FIXME: maybe use 64 bits? */ in mips_tr_init_disas_context()
15089 ctx->ulri = (env->CP0_Config3 >> CP0C3_ULRI) & 1; in mips_tr_init_disas_context()
15090 ctx->ps = ((env->active_fpu.fcr0 >> FCR0_PS) & 1) || in mips_tr_init_disas_context()
15091 (env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)); in mips_tr_init_disas_context()
15092 ctx->vp = (env->CP0_Config5 >> CP0C5_VP) & 1; in mips_tr_init_disas_context()
15093 ctx->mrp = (env->CP0_Config5 >> CP0C5_MRP) & 1; in mips_tr_init_disas_context()
15094 ctx->nan2008 = (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; in mips_tr_init_disas_context()
15095 ctx->abs2008 = (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; in mips_tr_init_disas_context()
15096 ctx->mi = (env->CP0_Config5 >> CP0C5_MI) & 1; in mips_tr_init_disas_context()
15097 ctx->gi = (env->CP0_Config5 >> CP0C5_GI) & 3; in mips_tr_init_disas_context()
15100 ctx->mem_idx = MIPS_HFLAG_UM; in mips_tr_init_disas_context()
15102 ctx->mem_idx = hflags_mmu_index(ctx->hflags); in mips_tr_init_disas_context()
15104 ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) && in mips_tr_init_disas_context()
15105 (ctx->insn_flags & (ISA_MIPS_R6 | in mips_tr_init_disas_context()
15114 if ((tb_cflags(ctx->base.tb) & CF_SINGLE_STEP) && in mips_tr_init_disas_context()
15115 (ctx->hflags & MIPS_HFLAG_BMASK)) { in mips_tr_init_disas_context()
15116 ctx->base.max_insns = 2; in mips_tr_init_disas_context()
15119 LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, in mips_tr_init_disas_context()
15120 ctx->hflags); in mips_tr_init_disas_context()
15131 tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK, in mips_tr_insn_start()
15132 ctx->btarget); in mips_tr_insn_start()
15142 is_slot = ctx->hflags & MIPS_HFLAG_BMASK; in mips_tr_translate_insn()
15143 if (ctx->insn_flags & ISA_NANOMIPS32) { in mips_tr_translate_insn()
15144 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15146 } else if (!(ctx->hflags & MIPS_HFLAG_M16)) { in mips_tr_translate_insn()
15147 ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15150 } else if (ctx->insn_flags & ASE_MICROMIPS) { in mips_tr_translate_insn()
15151 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15153 } else if (ctx->insn_flags & ASE_MIPS16) { in mips_tr_translate_insn()
15154 ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next); in mips_tr_translate_insn()
15158 g_assert(ctx->base.is_jmp == DISAS_NORETURN); in mips_tr_translate_insn()
15162 if (ctx->hflags & MIPS_HFLAG_BMASK) { in mips_tr_translate_insn()
15163 if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 | in mips_tr_translate_insn()
15171 if ((ctx->hflags & MIPS_HFLAG_M16) && in mips_tr_translate_insn()
15172 (ctx->hflags & MIPS_HFLAG_FBNSLOT)) { in mips_tr_translate_insn()
15183 if (ctx->base.is_jmp == DISAS_SEMIHOST) { in mips_tr_translate_insn()
15186 ctx->base.pc_next += insn_bytes; in mips_tr_translate_insn()
15188 if (ctx->base.is_jmp != DISAS_NEXT) { in mips_tr_translate_insn()
15194 * See mips_tr_init_disas_context about single-stepping a branch in mips_tr_translate_insn()
15197 if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE in mips_tr_translate_insn()
15198 && !(tb_cflags(ctx->base.tb) & CF_SINGLE_STEP)) { in mips_tr_translate_insn()
15199 ctx->base.is_jmp = DISAS_TOO_MANY; in mips_tr_translate_insn()
15207 switch (ctx->base.is_jmp) { in mips_tr_tb_stop()
15209 gen_save_pc(ctx->base.pc_next); in mips_tr_tb_stop()
15215 gen_goto_tb(ctx, 0, ctx->base.pc_next); in mips_tr_tb_stop()
15312 env->active_tc.PC = data[0]; in mips_restore_state_to_opc()
15313 env->hflags &= ~MIPS_HFLAG_BMASK; in mips_restore_state_to_opc()
15314 env->hflags |= data[1]; in mips_restore_state_to_opc()
15315 switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { in mips_restore_state_to_opc()
15321 env->btarget = data[2]; in mips_restore_state_to_opc()