| /qemu/include/hw/ppc/ |
| H A D | pnv_lpc.h | 94 * drive PSI SERIRQ irqs, routing according to OPB routing registers.
101 /* P9 serirq lines and irq routing table */
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| H A D | spapr_xive.h | 37 /* Routing table */
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| /qemu/hw/intc/ |
| H A D | arm_gicv3_dist.c | 309 /* This GIC implementation always has affinity routing enabled, in gicd_readb()
329 /* This GIC implementation always has affinity routing enabled, in gicd_writeb()
388 * NS affinity routing is enabled, otherwise RES0 in gicd_readl()
390 * NS affinity routing is not enabled, otherwise RES0 in gicd_readl()
391 * Since for QEMU affinity routing is always enabled in gicd_readl()
410 * LPIS == 1 (LPIs are supported if affinity routing is enabled) in gicd_readl()
500 /* RAZ/WI since affinity routing is always enabled */ in gicd_readl()
568 /* RAZ/WI since affinity routing is always enabled */ in gicd_readl()
619 * ARE is RAO/WI (affinity routing always on), and only in gicd_writel()
626 * ARE_NS and ARE_S are RAO/WI (affinity routing always on) in gicd_writel()
[all …]
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| H A D | arm_gicv3_kvm.c | 128 * corresponding to SPIs and PPIs are RAZ/WI when affinity routing
139 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 in kvm_dist_get_priority()
160 /* For the KVM GICv3, affinity routing is always enabled, and the first 8 in kvm_dist_put_priority()
182 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 in kvm_dist_get_edge_trigger()
207 /* For the KVM GICv3, affinity routing is always enabled, and the first 2 in kvm_dist_put_edge_trigger()
256 /* For the KVM GICv3, affinity routing is always enabled, and the in kvm_dist_getbmp()
278 /* For the KVM GICv3, affinity routing is always enabled, and the in kvm_dist_putbmp()
872 /* set up irq routing */ in kvm_arm_gicv3_realize()
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| H A D | bcm2836_control.c | 8 * At present, only implements interrupt routing, and mailboxes (i.e.,
87 /* apply routing logic, update status regs */ in bcm2836_control_update()
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| /qemu/include/hw/intc/ |
| H A D | bcm2836_control.h | 38 /* interrupt routing/control registers */
52 /* interrupt source registers, post-routing (also input-derived; visible) */
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| /qemu/docs/ |
| H A D | multiseat.txt | 9 multihead/multiseat and input event routing. Right now this
40 The "display=video2" sets up the input routing. Any input coming from
75 agent. But qemu can't figure it, so it can't do input routing.
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| H A D | pcie_sriov.txt | 36 Routing-ID Interpretation) capability to indicate that your device
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| /qemu/include/hw/southbridge/ |
| H A D | ich9.h | 27 * as ICH9 supports only D25-D31 irq routing.
30 * So fallback interrupt routing for any devices in any slots is necessary.
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| /qemu/include/hw/xen/ |
| H A D | xen-pvh-common.h | 39 * routing between INTX IRQ (0 - 3) and GSI's.
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| /qemu/include/semihosting/ |
| H A D | guestfd.h | 39 * For ARM semihosting, we have a separate structure for routing
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| /qemu/hw/isa/ |
| H A D | lpc_ich9.c | 115 /* the default irq routing is arbitrary as long as it matches with in ich9_cc_init()
116 * acpi irq routing table. in ich9_cc_init()
184 /* IRQ routing */
314 * routing to the PIC is disabled in the PIRQx_ROUT settings. in ich9_route_intx_pin_to_irq()
319 * disables the PIRQ routing even though it doesn't need to care. in ich9_route_intx_pin_to_irq()
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| H A D | vt82c686.c | 688 qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing %d for %d", in via_isa_set_irq()
819 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ in vt82c686b_isa_reset()
887 pci_conf[0x4c] = 0x04; /* IDE interrupt Routing */ in vt8231_isa_reset()
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| /qemu/docs/specs/ |
| H A D | ppc-xive.rst | 28 - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
30 routing by matching an event source number with an Event
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| H A D | rocker.rst | 716 30: unicast routing
717 40: multicast routing
756 unicast or multicast routing
761 Table ID 30: unicast routing::
776 Table ID 40: multicast routing::
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| /qemu/linux-user/mips/ |
| H A D | sockbits.h | 23 #define TARGET_SO_DONTROUTE 0x0010 /* Don't do local routing. */
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| /qemu/hw/i386/xen/ |
| H A D | xen-pvh.c | 97 * PCI INTX routing. in xen_pvh_machine_class_init()
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| /qemu/rust/hw/timer/hpet/src/ |
| H A D | device.rs | 101 /// Timer N Interrupt Routing Capability (bits 32:63)
306 // If the LegacyReplacement Route bit is set, the individual routing in get_int_route()
317 // routed as per the routing in the timer n config registers. in get_int_route()
320 // routing bits for each of the timers are used. in get_int_route()
553 /// Interrupt Routing Capability.
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| /qemu/hw/cpu/ |
| H A D | realview_mpcore.c | 77 /* ??? IRQ routing is hardcoded to "normal" mode. */ in realview_mpcore_realize()
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| /qemu/include/system/ |
| H A D | kvm.h | 120 * Returns: true if GSI routing is enabled (ie the kernel supports
143 * defining an MSI routing entry.
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| /qemu/hw/ppc/ |
| H A D | pnv_lpc.c | 428 /* Program the POWER9 LPC irq to PSI serirq routing table */
437 "OPB: setting serirq routing on POWER8 system, ignoring.\n"); in pnv_lpc_eval_serirq_routes()
471 * POWER9 and later have routing fields in OPB master registers that in pnv_lpc_eval_irqs()
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| /qemu/include/standard-headers/linux/ |
| H A D | pci_regs.h | 658 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
659 #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */
673 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
730 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
903 #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */
911 /* Alternative Routing-ID Interpretation */
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| /qemu/hw/misc/ |
| H A D | pc-testdev.c | 27 * as emulation, power management, interrupt routing, among others. It's meant
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| /qemu/include/hw/sd/ |
| H A D | sd.h | 204 * to them, selected by the guest reprogramming GPIO line routing.
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| /qemu/hw/m68k/ |
| H A D | q800-glue.c | 41 * The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes
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