Searched full:routed (Results 1 – 24 of 24) sorted by relevance
| /qemu/include/hw/intc/ |
| H A D | loongarch_extioi_common.h | 17 /* irq from EXTIOI is routed to no more than 4 cpus */
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| /qemu/docs/ |
| H A D | pci_expander_bridge.txt | 50 The interrupts from devices behind the PXB are routed through this device the same as if it were a
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| H A D | multiseat.txt | 41 the window which belongs to the video.2 display adapter will be routed
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| /qemu/target/arm/tcg/ |
| H A D | tlb_helper.c | 36 * ISV is only set for stage-2 data aborts routed to EL2 and in merge_syn_data_abort()
227 /* If SCR_EL3.GPF is unset, GPF may still be routed to EL2. */ in arm_deliver_fault()
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| /qemu/rust/hw/timer/hpet/src/ |
| H A D | device.rs | 303 // timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, in get_int_route()
304 // timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. in get_int_route()
317 // routed as per the routing in the timer n config registers. in get_int_route()
555 /// the timers' interrupt can be routed, and is encoded in the
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| /qemu/docs/system/i386/ |
| H A D | xen.rst | 51 can be routed to an event channel instead of to the emulated I/O or local
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| /qemu/python/qemu/qmp/ |
| H A D | qmp_client.py | 139 An execution reply was successfully routed, but not understood.
142 routed, but is otherwise malformed, this exception will be raised.
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| H A D | qmp_tui.py | 594 libraries begin used is routed to the screen.
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| /qemu/hw/ide/ |
| H A D | ich.c | 28 * Interrupt: pin B routed to IRQ 222
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| /qemu/hw/timer/ |
| H A D | hpet.c | 195 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, in update_irq()
196 * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. in update_irq()
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| /qemu/hw/pci-host/ |
| H A D | raven.c | 238 * Assignments", all PCI interrupts are routed via IRQ 15 in raven_pcihost_realizefn()
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| H A D | versatile.c | 30 * interrupts are going to be routed. So we start in state
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| H A D | astro.c | 541 /* find elroy to which this address is routed */ in adjust_LMMIO_DIRECT_mapping()
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| /qemu/hw/isa/ |
| H A D | lpc_ich9.c | 307 * Strictly speaking, this is wrong. The PIRQ should be routed in ich9_route_intx_pin_to_irq()
310 * routed according to the PIRQx_ROUT configuration. But QEMU in ich9_route_intx_pin_to_irq()
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| H A D | vt82c686.c | 700 /* ISA IRQ level is the OR of all sources routed to it */ in via_isa_set_irq()
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| /qemu/pc-bios/dtb/ |
| H A D | canyonlands.dts | 459 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
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| /qemu/docs/system/devices/ |
| H A D | cxl.rst | 84 which is routed to particular CXL Host Bridges. At time of generic
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| /qemu/hw/ppc/ |
| H A D | pnv_lpc.c | 443 * Each of the ISA irqs is routed to one of the 4 SERIRQ irqs with 2 in pnv_lpc_eval_serirq_routes()
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| /qemu/hw/audio/ |
| H A D | wm8750.c | 236 * connect both channels to where the left channel is routed. */ in wm8750_set_format()
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| /qemu/target/arm/ |
| H A D | cpu.c | 790 * If FIQs are routed to EL3 or EL2 then there are cases where in arm_excp_unmasked()
803 * when non-secure but only when FIQs are only routed to EL3. in arm_excp_unmasked()
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| H A D | helper.c | 6411 * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily
9786 * routed to EL3.
9788 * routed to EL2.
10414 /* IRQ routed to monitor mode */ in arm_cpu_do_interrupt_aarch32()
10425 /* FIQ routed to monitor mode */ in arm_cpu_do_interrupt_aarch32()
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| /qemu/hw/i386/kvm/ |
| H A D | xen_evtchn.c | 1651 * The event channel GSI cannot be routed to PIRQ, as that would make in xen_evtchn_set_gsi()
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| /qemu/target/i386/kvm/ |
| H A D | kvm.c | 6321 * If it was a PIRQ and successfully routed (handled == 0) or it was in kvm_arch_fixup_msi_route()
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| /qemu/ |
| H A D | qemu-options.hx | 3063 will be routed over the host to the outside. This option does
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