Searched +full:riscv +full:- +full:j +full:- +full:extension (Results 1 – 9 of 9) sorted by relevance
| /linux-6.15/Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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| /linux-6.15/arch/riscv/kernel/ |
| D | cpufeature.c | 1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
42 /* Per-cpu ISA extensions. */
48 * riscv_isa_extension_base() - Get base extension word
51 * Return: base extension word as unsigned long value
62 * __riscv_isa_extension_available() - Check whether given extension
66 * @bit: bit position of the desired extension
88 return -EPROBE_DEFER; in riscv_ext_f_depends()
95 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_ext_zicbom_validate()
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| /linux-6.15/arch/riscv/mm/ |
| D | cacheflush.c | 1 // SPDX-License-Identifier: GPL-2.0-only
35 * Performs an icache flush for the given MM context. RISC-V has no direct
39 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
52 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
65 if (mm == current->active_mm && local) { in flush_icache_mm()
91 if (!test_bit(PG_dcache_clean, &folio->flags)) { in flush_icache_pte()
93 set_bit(PG_dcache_clean, &folio->flags); in flush_icache_pte()
136 /* set block-size for cbom and/or cboz extension if available */ in riscv_init_cbo_blocksizes()
137 cbo_get_block_size(node, "riscv,cbom-block-size", in riscv_init_cbo_blocksizes()
139 cbo_get_block_size(node, "riscv,cboz-block-size", in riscv_init_cbo_blocksizes()
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| /linux-6.15/scripts/bash-completion/ |
| D | make | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # bash completion for GNU make with kbuild extension -*- shell-script -*-
5 # /usr/share/bash-completion/completions/make, but we do not rely on it.
8 …local -a dirs=("${BASH_COMPLETION_USER_DIR:-${XDG_DATA_HOME:-$HOME/.local/share}/bash-completion}/…
11 for dir in ${XDG_DATA_DIRS:-/usr/local/share:/usr/share}; do
12 dirs+=("$dir"/bash-completion/completions)
19 if [[ ! -d ${dir} || ${dir} = "${this_dir}" ]]; then
26 if [[ -f ${compfile} ]] && . "${compfile}" &>/dev/null; then
30 set -- $(complete -p make)
32 while [[ $# -gt 1 && "$1" != -F ]]; do
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| /linux-6.15/drivers/perf/ |
| D | riscv_pmu_sbi.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * RISC-V performance counter support.
11 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
62 PMU_FORMAT_ATTR(event, "config:0-47");
63 PMU_FORMAT_ATTR(firmware, "config:62-63");
90 * RISC-V doesn't have heterogeneous harts yet. This need to be part of
306 0, cmask, 0, edata->event_idx, 0, 0); in pmu_sbi_check_event()
312 edata->event_idx = -ENOENT; in pmu_sbi_check_event()
322 for (int j = 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) in pmu_sbi_check_std_events() local
323 for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) in pmu_sbi_check_std_events()
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| /linux-6.15/crypto/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
177 bool "Disable run-time self tests"
180 Disable run-time self tests that normally take place at
184 bool "Enable extra run-time crypto self tests"
187 Enable extra run-time self tests of registered crypto algorithms,
246 profile. This is required for Kerberos 5-style encryption, used by
265 menu "Public-key cryptography"
268 tristate "RSA (Rivest-Shamir-Adleman)"
275 RSA (Rivest-Shamir-Adleman) public key algorithm (RFC8017)
278 tristate "DH (Diffie-Hellman)"
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| /linux-6.15/drivers/spi/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
52 bool "SPI memory extension"
54 Enable this option if you want to enable the SPI memory extension.
55 This extension is meant to simplify interaction with SPI memories
56 by providing a high-level interface to send memory-like commands.
69 This enables support for SPI-NAND mode on the Airoha NAND
71 is implemented as a SPI-MEM controller.
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| /linux-6.15/Documentation/admin-guide/ |
| D | kernel-parameters.txt | 16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nocmcff -- Disable firmware first mode for corrected
28 nospcr -- disable console in ACPI SPCR table as
45 If set to vendor, prefer vendor-specific driver
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| /linux-6.15/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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