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/qemu/qapi/
H A Dcxl.json394 # Revision 3.1, Table 7-70.
435 # Revision 3.1, Section 7.6.7.6.5. Note that, currently, establishing
442 # (CXL) Specification, Revision 3.1, Table 7-70.
445 # Compute Express Link (CXL) Specification, Revision 3.1,
450 # Link (CXL) Specification, Revision 3.1, Table 7-70. Valid
454 # Specification, Revision 3.1, Table 7-70.
457 # (CXL) Specification, Revision 3.1, Table 7-70.
481 # Specification, Revision 3.1, Table 7-71.
501 # Specification, Revision 3.1, Section 7.6.7.6.6. Note that,
508 # (CXL) Specification, Revision 3.1, Table 7-71.
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H A Dacpi.json33 # @rev: table revision number (dependent on signature, 1 byte)
39 # @oem_rev: OEM-supplied revision number (4 bytes)
44 # @asl_compiler_rev: revision number of the utility that created the
/qemu/include/hw/cxl/
H A Dcxl_pci.h75 * DVSEC ID: 0, Revision: 3
101 * DVSEC ID: 3, Revision: 0
126 * DVSEC ID: 4, Revision: 0
138 * DVSEC ID: 5, Revision 0
150 * DVSEC ID: 7, Revision 2
166 * DVSEC ID: 8, Revision 0
/qemu/tests/qtest/
H A Dacpi-utils.c55 uint8_t revision; in acpi_fetch_rsdp_table() local
57 /* Read mandatory revision 0 table data (20 bytes) first */ in acpi_fetch_rsdp_table()
59 revision = rsdp_table[15 /* Revision offset */]; in acpi_fetch_rsdp_table()
61 switch (revision) { in acpi_fetch_rsdp_table()
/qemu/hw/usb/
H A Dhcd-ehci-pci.c29 uint8_t revision; member
189 k->revision = i->revision; in ehci_data_class_init()
201 .revision = 0x10,
206 .revision = 0x03,
212 .revision = 0x03,
/qemu/hw/intc/
H A Darm_gic_common.c174 s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100); in gic_init_irqs_and_mmio()
217 (s->revision == REV_11MPCORE)) { in arm_gic_common_realize()
218 error_setg(errp, "this GIC revision does not implement " in arm_gic_common_realize()
224 if (s->revision != 2) { in arm_gic_common_realize()
226 "supported by revision 2"); in arm_gic_common_realize()
244 if (s->revision == REV_11MPCORE) { in arm_gic_common_reset_irq_state()
355 /* Revision can be 1 or 2 for GIC architecture specification
358 DEFINE_PROP_UINT32("revision", GICState, revision, 1),
H A Darm_gic.c77 return s->revision == 2 || s->security_extn; in gic_has_groups()
412 if (s->revision == REV_11MPCORE) { in gic_set_irq()
623 if (s->revision == REV_11MPCORE) { in gic_acknowledge_irq()
753 if (s->revision == 2) { in gic_set_cpu_control()
759 if (s->revision == 2) { in gic_set_cpu_control()
774 if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { in gic_get_running_priority()
799 if (s->revision != 2) { in gic_eoi_split()
912 if (s->revision == REV_11MPCORE) { in gic_complete_irq()
1052 } else if (s->revision == 2) { in gic_dist_readb()
1080 if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { in gic_dist_readb()
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H A Darm_gicv3_common.c152 return cs->gic->revision > 3; in gicv4_needed()
378 * on the GIC revision: notably, the in-kernel KVM GIC doesn't in arm_gicv3_common_realize()
381 if (s->revision != 3 && s->revision != 4) { in arm_gicv3_common_realize()
382 error_setg(errp, "unsupported GIC revision %d", s->revision); in arm_gicv3_common_realize()
472 if (s->revision > 3) { in arm_gicv3_common_realize()
611 DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
/qemu/hw/i2c/
H A Domap_i2c.c39 uint8_t revision; member
167 return s->revision; /* REV */ in omap_i2c_read()
176 if (s->revision >= OMAP2_INTR_REV) in omap_i2c_read()
277 s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f); in omap_i2c_write()
281 if (s->revision < OMAP2_INTR_REV) { in omap_i2c_write()
325 if (s->revision < OMAP2_INTR_REV) { in omap_i2c_write()
338 if (s->revision < OMAP2_INTR_REV) { in omap_i2c_write()
393 if (s->revision >= OMAP2_INTR_REV) { in omap_i2c_write()
491 (s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000); in omap_i2c_realize()
497 if (s->revision >= OMAP2_INTR_REV && !s->iclk) { in omap_i2c_realize()
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/qemu/docs/specs/
H A Divshmem-spec.rst23 The device has vendor ID 1af4, device ID 1110, revision 1. Before
24 QEMU 2.6.0, it had revision 0.
49 revision 0 rather than 1. Guest software should wait for the
53 Revision 0 of the device is not capable to tell guest software whether
82 In revision 0 of the device, Interrupt Status and Mask Register
93 reset. These devices have PCI revision 0 rather than 1.
118 If the peer is a revision 0 device without MSI-X capability, its
H A Dacpi_nvdimm.rst51 An Integer containing the Revision ID (4 Bytes)
56 UUID, Revision ID, and Function Index
61 Otherwise, the return value and type depends on the UUID, revision ID
111 4 bytes, Revision ID, that is the Arg1 of _DSM method.
189 Revision ID (set to 1)
/qemu/hw/s390x/
H A Dvirtio-ccw.c115 VMSTATE_INT32(revision, VirtioCcwDevice),
197 uint16_t revision; member
339 if (dev->revision < 0 && ccw.cmd_code != CCW_CMD_SET_VIRTIO_REV) { in virtio_ccw_cb()
342 * virtio-1 drivers must start with negotiating to a revision >= 1, in virtio_ccw_cb()
351 dev->revision = 0; in virtio_ccw_cb()
358 ret = virtio_ccw_handle_set_vq(sch, ccw, check_len, dev->revision < 1); in virtio_ccw_cb()
386 if (dev->revision >= 1) { in virtio_ccw_cb()
393 } else if ((features.index == 1) && (dev->revision >= 1)) { in virtio_ccw_cb()
396 * negotiated at least revision 1. in virtio_ccw_cb()
434 } else if ((features.index == 1) && (dev->revision >= 1)) { in virtio_ccw_cb()
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H A Dvirtio-ccw.h70 int revision; member
84 /* The maximum virtio revision we support. */
/qemu/hw/i386/xen/
H A Dxen_pvdevice.c51 uint8_t revision; member
103 pci_set_byte(pci_conf + PCI_REVISION_ID, d->revision); in xen_pv_realize()
121 DEFINE_PROP_UINT8("revision", XenPVDevice, revision, 0x01),
/qemu/hw/arm/
H A Draspi.c48 * Board revision codes:
49 * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/
51 FIELD(REV_CODE, REVISION, 0, 4);
321 mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)", in raspi_machine_class_common_init()
323 FIELD_EX32(board_rev, REV_CODE, REVISION)); in raspi_machine_class_common_init()
346 rmc->board_rev = 0x920092; /* Revision 1.2 */ in raspi0_machine_class_init()
356 rmc->board_rev = 0x900021; /* Revision 1.1 */ in raspi1ap_machine_class_init()
377 rmc->board_rev = 0x9020e0; /* Revision 1.0 */ in raspi3ap_machine_class_init()
H A Draspi4b.c116 rmc->board_rev = 0xa03111; /* Revision 1.1, 1 Gb RAM */ in raspi4b_machine_class_init()
118 rmc->board_rev = 0xb03115; /* Revision 1.5, 2 Gb RAM */ in raspi4b_machine_class_init()
/qemu/linux-user/arm/
H A Dtarget_proc.h26 midr_rev = FIELD_EX32(cpu->midr, MIDR_EL1, REVISION); in open_cpuinfo()
88 dprintf(fd, "CPU revision\t: %d\n\n", midr_rev); in open_cpuinfo()
94 dprintf(fd, "Revision\t: 0000\n"); in open_cpuinfo()
/qemu/hw/acpi/
H A Dtrace-events88 acpi_nvdimm_dsm_info(uint32_t revision, uint32_t handle, uint32_t function) "Revision 0x%" PRIx32 "…
89 acpi_nvdimm_invalid_revision(uint32_t revision) "Revision 0x%" PRIx32 " is not supported, expect 0x…
/qemu/hw/riscv/
H A Driscv-iommu-pci.c66 uint8_t revision; member
92 pci_set_byte(pci_conf + PCI_REVISION_ID, s->revision); in riscv_iommu_pci_realize()
168 DEFINE_PROP_UINT8("revision", RISCVIOMMUStatePci, revision, 0x01),
H A Dvirt-acpi-build.c273 * ACPI spec, Revision 6.5+
329 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ in build_rhct()
344 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ in build_rhct()
374 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ in build_rhct()
406 build_append_int_noprefix(table_data, 0x1, 2); /* Revision */ in build_rhct()
511 * ACPI spec, Revision 6.5+
731 build_append_int_noprefix(table_data, 1, 1); /* Revision */ in build_rimt()
780 build_append_int_noprefix(table_data, 1, 1); /* Revision */ in build_rimt()
815 * ACPI spec, Revision 6.5+
927 .revision = 2, in virt_acpi_build()
/qemu/linux-user/alpha/
H A Dtarget_proc.h38 "cpu revision\t\t: 0\n" in open_cpuinfo()
42 "system revision\t\t: 0\n" in open_cpuinfo()
/qemu/hw/cxl/
H A Dswitch-mailbox-cci.c9 * Compute Express Link (CXL) Specification revision 3.0 Version 1.0
91 pc->revision = 0; in cswmbcci_class_init()
/qemu/hw/net/
H A Deepro100.c140 uint8_t revision; member
305 /* BITS(10, 8) device revision */
580 logout("Get device id and revision from EEPROM!!!\n"); in e100_pci_reset()
1906 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1907 .revision = 0x0e,
1918 /* Revision ID: 0x0f, 0x10. */
1919 .revision = 0x0f,
1929 .revision = 0x01,
1936 .revision = 0x02,
1943 .revision = 0x03,
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/qemu/include/hw/acpi/
H A Dacpi-defs.h45 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */ member
69 uint8_t rev; /* Revision */
/qemu/target/mips/tcg/
H A Drel6.decode10 # The MIPS32 Instruction Set Reference Manual, Revision 6.06
14 # The MIPS64 Instruction Set Reference Manual, Revision 6.06

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