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/linux/Documentation/devicetree/bindings/rtc/
H A Dingenic,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Real-Time Clock
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: rtc.yaml#
14 - if:
20 - ingenic,jz4770-rtc
21 - ingenic,jz4780-rtc
24 "#clock-cells": false
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dti,tas5086.txt1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
11 chip's !RESET pin. If specified, the driver will
12 assert a hardware reset at probe time.
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
17 waits for this period of time before starting the
[all …]
/linux/drivers/pps/clients/
H A Dpps-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pps-gpio.c -- PPS client driver using GPIO
9 #define PPS_GPIO_NAME "pps-gpio"
33 struct timer_list echo_timer; /* timer to reset echo active state */
50 /* Get the time stamp first */ in pps_gpio_irq_handler()
56 rising_edge = info->capture_clear ? in pps_gpio_irq_handler()
57 gpiod_get_value(info->gpio_pin) : !info->assert_falling_edge; in pps_gpio_irq_handler()
58 if ((rising_edge && !info->assert_falling_edge) || in pps_gpio_irq_handler()
59 (!rising_edge && info->assert_falling_edge)) in pps_gpio_irq_handler()
60 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
[all …]
/linux/arch/mips/include/asm/sn/
H A Dioc3.h1 /* SPDX-License-Identifier: GPL-2.0 */
50 u8 fill0[0x151 - 0x142 - 1];
56 u8 fill1[0x159 - 0x153 - 1];
62 u8 fill2[0x16a - 0x15b - 1];
67 u8 fill3[0x170 - 0x16b - 1];
153 u32 pad1[(0x20000 - 0x00154) / 4];
157 u32 pad2[(0x40000 - 0x20180) / 4];
160 u32 ssram[(0x80000 - 0x40000) / 4];
163 0x80000 - Access to the generic devices selected with DEV0
165 0xA0000 - Access to the generic devices selected with DEV1
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
11 chassis-type = "tablet";
16 pp1250_s3: regulator-pp1250-s3 {
17 compatible = "regulator-fixed";
18 regulator-name = "pp1250_s3";
21 regulator-always-on;
22 regulator-boot-on;
23 regulator-min-microvolt = <1250000>;
[all …]
/linux/lib/zstd/compress/
H A Dzstd_compress_internal.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
19 /*-*************************************
27 /*-*************************************
41 /*-*************************************
86 U16 mlBase; /* mlBase == matchLength - MINMATCH */
127 seqLen.litLength = seq->litLength; in ZSTD_getSequenceLength()
128 seqLen.matchLength = seq->mlBase + MINMATCH; in ZSTD_getSequenceLength()
129 if (seqStore->longLengthPos == (U32)(seq - seqStore->sequencesStart)) { in ZSTD_getSequenceLength()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dpm3393.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
14 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
87 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
93 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
97 /* Port reset. */
115 /* PM3393 - Enabling all hardware block interrupts. in pm3393_interrupt_enable()
138 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
144 /* TERMINATOR - PL_INTERRUPTS_EXT */ in pm3393_interrupt_enable()
145 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
[all …]
/linux/drivers/pci/controller/
H A Dpcie-mediatek-gen3.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <linux/irqchip/irq-msi-lib.h>
30 #include <linux/reset.h>
79 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
83 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
87 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
121 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
133 /* Time in ms needed to complete PCIe reset on EN7581 SoC */
149 * struct mtk_gen3_pcie_pdata - differentiate between host generations
[all …]
H A Dpci-aardvark.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/irqchip/irq-msi-lib.h>
21 #include <linux/pci-ecam.h>
30 #include "../pci-bridge-emul.h"
140 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
294 writel(val, pcie->base + reg); in advk_writel()
299 return readl(pcie->base + reg); in advk_readl()
314 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
322 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
336 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_training()
[all …]
/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
44 #define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */
45 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
49 /* Physical Func Reset Done Indication */
62 /* Interrupt acknowledge Auto-mask */
91 #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
183 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
[all …]
/linux/drivers/macintosh/
H A Dvia-cuda.c1 // SPDX-License-Identifier: GPL-2.0
7 * This MCU controls system power, Parameter RAM, Real Time Clock and the
38 /* VIA registers - spaced 0x200 bytes apart */
40 #define B 0 /* B-side data */
41 #define A RS /* A-side data */
42 #define DIRB (2*RS) /* B-side direction (1=output) */
43 #define DIRA (3*RS) /* A-side direction (1=output) */
55 #define ANH (15*RS) /* A-side data, no handshake */
61 * VIA pin | Egret pin
62 * ----------------+------------------------------------------
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
143 CS_MRST_CLR = 1<<3, /* Clear Master reset */
144 CS_MRST_SET = 1<<2, /* Set Master reset */
145 CS_RST_CLR = 1<<1, /* Clear Software reset */
146 CS_RST_SET = 1, /* Set Software reset */
217 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
223 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
[all …]
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
172 * This value is in terms of 32-bit words.
181 * @rsttype: Reset Style for Clocked always Blocks in RTL (RstType)
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-ux500-samsung-skomer.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Devicetree for the Samsung XCover 2 GT-S7710 also known as Skomer.
6 /dts-v1/;
7 #include "ste-db8500.dtsi"
8 #include "ste-ab8505.dtsi"
9 #include "ste-dbx5x0-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
[all …]
H A Dste-ux500-samsung-kyle.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Devicetree for the Samsung Galaxy Amp SGH-I407 also known as Kyle.
10 /dts-v1/;
11 #include "ste-db8500.dtsi"
12 #include "ste-ab8505.dtsi"
13 #include "ste-dbx5x0-pinctrl.dtsi"
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
[all …]
/linux/drivers/iio/light/
H A Drpr0521.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RPR-0521 ROHM Ambient Light and Proximity Sensor
7 * IIO driver for RPR-0521RS (7-bit I2C slave address 0x38).
32 #define RPR0521_REG_PXS_DATA 0x44 /* 16-bit, little endian */
33 #define RPR0521_REG_ALS_DATA0 0x46 /* 16-bit, little endian */
34 #define RPR0521_REG_ALS_DATA1 0x48 /* 16-bit, little endian */
69 #define RPR0521_DEFAULT_MEAS_TIME 0x06 /* ALS - 100ms, PXS - 100ms */
169 {2, 500000, 20, 0}, /* 1000, measurement 100ms, sleep 300ms */
170 {2, 500000, 10, 0}, /* 1001, measurement 100ms, sleep 300ms */
189 /* optimize runtime pm ops - enable/disable device only if needed */
[all …]
/linux/drivers/net/fddi/skfp/h/
H A Dsupern_2.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
48 #define FS_SSRCRTG (1<<12) /* if SA has set MSB (source-routing)*/
54 #define FS_SFRMTY2 (1<<6) /* frame-class bit */
55 #define FS_SFRMTY1 (1<<5) /* frame-type bit (impementor) */
56 #define FS_SFRMTY0 (1<<4) /* frame-type bit (LLC) */
58 #define FS_ERFBB0 (1<<0) /* - " - */
95 unsigned int rx_sadrrg :1 ; /* DA == MA or broad-/multicast */
97 unsigned int rx_seac0 :1 ; /* frame-copied C-indicator */
98 unsigned int rx_seac1 :1 ; /* address-match A-indicator */
99 unsigned int rx_seac2 :1 ; /* frame-error E-indicator */
[all …]
/linux/drivers/net/phy/
H A Dsmsc.c1 // SPDX-License-Identifier: GPL-2.0+
27 /* Vendor-specific PHY Definitions */
28 /* EDPD NLP / crossover time configuration */
39 /* interval between phylib state machine runs in ms */
70 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in smsc_phy_config_intr()
91 struct smsc_phy_priv *priv = phydev->priv; in smsc_phy_config_edpd()
93 if (priv->edpd_enable) in smsc_phy_config_edpd()
107 if (irq_status != -ENODEV) in smsc_phy_handle_interrupt()
124 struct smsc_phy_priv *priv = phydev->priv; in smsc_phy_config_init()
130 if (!priv->edpd_mode_set_by_user && phydev->irq != PHY_POLL) in smsc_phy_config_init()
[all …]
/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
89 * e1000_set_phy_type - Set the phy type member in the hw struct.
94 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
95 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
97 switch (hw->phy_id) { in e1000_set_phy_type()
103 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
106 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
107 hw->mac_type == e1000_82541_rev_2 || in e1000_set_phy_type()
108 hw->mac_type == e1000_82547 || in e1000_set_phy_type()
[all …]
/linux/drivers/net/pse-pd/
H A Dtps23881.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/pse-pd/pse.h>
94 * @param chan: The channel number (0-7).
114 * @param chan: The channel number (0-7).
141 struct i2c_client *client = priv->client; in tps23881_pi_set_pw_pol_limit()
146 chan = priv->port[id].chan[0]; in tps23881_pi_set_pw_pol_limit()
167 struct i2c_client *client = priv->client; in tps23881_pi_enable_manual_pol()
180 chan = priv->port[id].chan[0]; in tps23881_pi_enable_manual_pol()
188 struct i2c_client *client = priv->client; in tps23881_pi_enable()
194 return -ERANGE; in tps23881_pi_enable()
[all …]
/linux/drivers/net/ethernet/sun/
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
104 len of non-reassembly pkt
183 #define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
185 #define BIM_CFG_32BIT 0x010 /* (ro) 1 = 32-bit slot, 0 = 64-bit */
191 reset. reserved in Cassini. */
[all …]
/linux/drivers/media/i2c/
H A Dar0521.c1 // SPDX-License-Identifier: GPL-2.0
4 * - Przemysłowy Instytut Automatyki i Pomiarów PIAP
12 #include <media/v4l2-ctrls.h>
13 #include <media/v4l2-fwnode.h>
14 #include <media/v4l2-subdev.h>
145 return &container_of(ctrl->handler, struct ar0521_dev, in ctrl_to_sd()
146 ctrls.handler)->sd; in ctrl_to_sd()
156 return div_u64(v + d - 1, d); in div64_round_up()
161 switch (sensor->fmt.code) { in ar0521_code_to_bpp()
166 return -EINVAL; in ar0521_code_to_bpp()
[all …]
/linux/fs/ocfs2/dlm/
H A Ddlmmaster.c1 // SPDX-License-Identifier: GPL-2.0-or-later
58 if (dlm != mle->dlm) in dlm_mle_equal()
61 if (namelen != mle->mnamelen || in dlm_mle_equal()
62 memcmp(name, mle->mname, namelen) != 0) in dlm_mle_equal()
118 case -EBADF: in dlm_is_host_down()
119 case -ECONNREFUSED: in dlm_is_host_down()
120 case -ENOTCONN: in dlm_is_host_down()
121 case -ECONNRESET: in dlm_is_host_down()
122 case -EPIPE: in dlm_is_host_down()
123 case -EHOSTDOWN: in dlm_is_host_down()
[all …]
/linux/drivers/net/ethernet/sfc/falcon/
H A Dfalcon.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
134 (*(u32 *)((efx)->stats_buffer.addr + XgDmaDone_offset))
139 /* 48-bit stats are zero-padded to 64 on DMA */ \
199 [0 ... BITS_TO_LONGS(FALCON_STAT_COUNT) - 1] = ~0UL,
211 #define SPI_WRDI 0x04 /* Reset write enable latch */
216 #define SPI_STATUS_WPEN 0x80 /* Write-protect pin enabled */
225 * Non-volatile memory layout
231 * 0-0x400 chip and board config (see struct falcon_nvconfig)
[all …]

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