| /linux-5.10/arch/arm/boot/dts/ |
| D | r8a7778-bockw.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Reference Device Tree Source for the R-Car M1A (R8A77781) Bock-W board
14 /dts-v1/;
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/gpio/gpio.h>
29 stdout-path = "serial0:115200n8";
34 reg = <0x60000000 0x10000000>;
37 fixedregulator3v3: regulator-3v3 {
38 compatible = "regulator-fixed";
39 regulator-name = "fixed-3.3V";
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| D | r8a73a4.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/r8a73a4-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a15";
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| D | bcm21664.dtsi | 14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
17 #include "dt-bindings/clock/bcm21664.h"
20 #address-cells = <1>;
21 #size-cells = <1>;
24 interrupt-parent = <&gic>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a9";
37 reg = <0>;
[all …]
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| D | imx7d-sdb.dts | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 /dts-v1/;
11 compatible = "fsl,imx7d-sdb", "fsl,imx7d";
14 stdout-path = &uart1;
19 reg = <0x80000000 0x80000000>;
22 gpio-keys {
23 compatible = "gpio-keys";
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_gpio_keys>;
27 volume-up {
[all …]
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| D | am57-pruss.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
9 pruss1_tm: target-module@4b226000 {
10 compatible = "ti,sysc-pruss", "ti,sysc";
11 reg = <0x4b226000 0x4>,
13 reg-names = "rev", "sysc";
14 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT |
16 ti,sysc-midle = <SYSC_IDLE_FORCE>,
19 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
24 clock-names = "fck";
[all …]
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| D | stm32mp157c-ed1.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxaa-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/mfd/st,stpmic1.h>
17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
20 stdout-path = "serial0:115200n8";
25 reg = <0xC0000000 0x40000000>;
[all …]
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| D | atlas6-evb.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
14 compatible = "sirf,atlas6-cb", "sirf,atlas6";
18 reg = <0x00000000 0x20000000>;
22 peri-iobg {
24 pinctrl-names = "default";
25 pinctrl-0 = <&uart1_pins_a>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&spi0_pins_a>;
33 reg = <0>;
[all …]
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| D | stm32mp15xx-dhcom-pdk2.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/pwm/pwm.h>
17 stdout-path = "serial0:115200n8";
20 clk_ext_audio_codec: clock-codec {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
26 display_bl: display-bl {
[all …]
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| D | kirkwood-openblocks_a6.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6282.dtsi"
9 compatible = "plathome,openblocks-a6", "marvell,kirkwood-88f6283", "marvell,kirkwood";
13 reg = <0x00000000 0x20000000>;
18 stdout-path = &uart0;
31 nr-ports = <1>;
40 reg = <0x30>;
44 pinctrl: pin-controller@10000 {
45 pinctrl-0 = <&pmx_dip_switches>;
[all …]
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| D | armada-370-dlink-dns327l.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for D-Link DNS-327L
12 /dts-v1/;
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include "armada-370.dtsi"
19 model = "D-Link DNS-327L";
22 "marvell,armada-370-xp";
25 stdout-path = &uart0;
30 reg = <0x00000000 0x20000000>; /* 512 MiB */
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/phy/ |
| D | qcom,usb-hs-28nm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
18 - qcom,usb-hs-28nm-femtophy
20 reg:
23 "#phy-cells":
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | rockchip-spdif.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-spdif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Heiko Stuebner <heiko@sntech.de>
20 - const: rockchip,rk3066-spdif
21 - const: rockchip,rk3228-spdif
22 - const: rockchip,rk3328-spdif
23 - const: rockchip,rk3366-spdif
24 - const: rockchip,rk3368-spdif
[all …]
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| D | adi,axi-spdif-tx.txt | 1 ADI AXI-SPDIF controller
4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
5 - reg : Must contain SPDIF core's registers location and length
6 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
11 - dmas: Pairs of phandle and specifier for the DMA channel that is used by
13 - dma-names : Must be "tx"
15 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
17 * resource-names.txt
18 * clock/clock-bindings.txt
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| /linux-5.10/arch/arc/boot/dts/ |
| D | axs10x_mb.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
23 reg = <0x11220 0x4>;
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/media/ |
| D | qcom,sc7180-venus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/qcom,sc7180-venus.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
19 const: qcom,sc7180-venus
21 reg:
27 power-domains:
31 power-domain-names:
35 - const: venus
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/remoteproc/ |
| D | ti,davinci-rproc.txt | 4 Binding status: Unstable - Subject to changes for DT representation of clocks
7 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
8 is used to offload some of the processor-intensive tasks or algorithms, for
11 The processor cores in the sub-system usually contain additional sub-modules
18 Each DSP Core sub-system is represented as a single DT node.
21 --------------------
24 - compatible: Should be one of the following,
25 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
27 - reg: Should contain an entry for each value in 'reg-names'.
30 the parent node's '#address-cells' and '#size-cells' values.
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/spi/ |
| D | allwinner,sun4i-a10-spi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/allwinner,sun4i-a10-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "spi-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
21 const: allwinner,sun4i-a10-spi
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/mfd/ |
| D | atmel-hlcdc.txt | 1 Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver
4 - compatible: value should be one of the following:
5 "atmel,at91sam9n12-hlcdc"
6 "atmel,at91sam9x5-hlcdc"
7 "atmel,sama5d2-hlcdc"
8 "atmel,sama5d3-hlcdc"
9 "atmel,sama5d4-hlcdc"
10 "microchip,sam9x60-hlcdc"
11 - reg: base address and size of the HLCDC device registers.
12 - clock-names: the name of the 3 clocks requested by the HLCDC device.
[all …]
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| /linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | imx8mq-evk.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 /dts-v1/;
13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
16 stdout-path = &uart1;
21 reg = <0x00000000 0x40000000 0 0xc0000000>;
24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <100000000>;
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | clk-exynos-audss.txt | 9 - compatible: should be one of the following:
10 - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
11 - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
13 - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
15 - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
17 - reg: physical base address and length of the controller's register set.
19 - #clock-cells: should be 1.
21 - clocks:
22 - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
24 - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/serial/ |
| D | fsl-mxs-auart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-mxs-auart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <fabio.estevam@nxp.com>
13 - $ref: "serial.yaml"
18 - fsl,imx23-auart
19 - fsl,imx28-auart
20 - alphascale,asm9260-auart
22 reg:
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | allwinner,sun4i-a10-nand.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "nand-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
22 - allwinner,sun4i-a10-nand
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra124-xusb.txt | 8 --------------------
9 - compatible: Must be:
10 - Tegra124: "nvidia,tegra124-xusb"
11 - Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
12 - Tegra210: "nvidia,tegra210-xusb"
13 - Tegra186: "nvidia,tegra186-xusb"
14 - reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
16 - reg-names: Must contain the following entries:
17 - "hcd"
18 - "fpci"
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | synopsys-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "synopsys-dw-mshc-common.yaml#"
13 - Ulf Hansson <ulf.hansson@linaro.org>
18 const: snps,dw-mshc
20 reg:
33 clock-names:
35 - const: biu
[all …]
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| /linux-5.10/drivers/clk/sunxi/ |
| D | clk-sun8i-bus-gates.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on clk-simple-gates.c, which is:
8 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/clk-provider.h>
22 static const char * const names[] = { "ahb1", "ahb2", "apb1", "apb2" }; in sun8i_h3_bus_gates_init() local
30 void __iomem *reg; in sun8i_h3_bus_gates_init() local
36 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); in sun8i_h3_bus_gates_init()
37 if (IS_ERR(reg)) in sun8i_h3_bus_gates_init()
40 for (i = 0; i < ARRAY_SIZE(names); i++) { in sun8i_h3_bus_gates_init()
41 int idx = of_property_match_string(node, "clock-names", in sun8i_h3_bus_gates_init()
[all …]
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