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/linux-5.10/Documentation/devicetree/bindings/usb/
Datmel-usb.txt6 - compatible: Should be "atmel,at91rm9200-ohci" for USB controllers
8 - reg: Address and length of the register set for the device
9 - interrupts: Should contain ohci interrupt
10 - clocks: Should reference the peripheral, host and system clocks
11 - clock-names: Should contain three strings
15 - num-ports: Number of ports.
16 - atmel,vbus-gpio: If present, specifies a gpio that needs to be
18 - atmel,oc-gpio: If present, specifies a gpio that needs to be
22 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
23 reg = <0x00500000 0x100000>;
[all …]
Dmediatek,mtk-xhci.txt6 the second one supports dual-role mode, and the host is based on xHCI
11 ------------------------------------------------------------------------
14 - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
15 soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
16 "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
18 - "mediatek,mt8173-xhci"
19 - reg : specifies physical base address and size of the registers
20 - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
21 - interrupts : interrupt used by the controller
22 - power-domains : a phandle to USB power domain node to control USB's
[all …]
/linux-5.10/arch/arm/boot/dts/
Dr8a7792-wheat.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
24 stdout-path = "serial0:115200n8";
29 reg = <0 0x40000000 0 0x40000000>;
32 d3_3v: regulator-3v3 {
33 compatible = "regulator-fixed";
34 regulator-name = "D3.3V";
35 regulator-min-microvolt = <3300000>;
[all …]
Dstm32mp15xx-dhcor-avenger96.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
9 #include "stm32mp15xx-dhcor-io1v8.dtsi"
22 cec_clock: clk-cec-fixed {
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
29 stdout-path = "serial0:115200n8";
32 hdmi-out {
33 compatible = "hdmi-connector";
[all …]
Dr8a7791-porter.dts1 // SPDX-License-Identifier: GPL-2.0
9 * SSI-AK4642
11 * JP3: 2-1: AK4642
12 * 2-3: ADV7511
19 /dts-v1/;
21 #include <dt-bindings/gpio/gpio.h>
35 stdout-path = "serial0:115200n8";
40 reg = <0 0x40000000 0 0x40000000>;
45 reg = <2 0x00000000 0 0x40000000>;
48 vcc_sdhi0: regulator-vcc-sdhi0 {
[all …]
Dr8a7790-lager.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
7 * Copyright (C) 2015-2016 Renesas Electronics Corporation
11 * SSI-AK4643
38 /dts-v1/;
40 #include <dt-bindings/gpio/gpio.h>
41 #include <dt-bindings/input/input.h>
60 stdout-path = "serial0:115200n8";
65 reg = <0 0x40000000 0 0x40000000>;
70 reg = <1 0x40000000 0 0xc0000000>;
[all …]
Dste-ab8500.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/ste-ab8500.h>
10 iio-hwmon {
11 compatible = "iio-hwmon";
12 io-channels = <&gpadc 0x02>, /* Battery temperature */
27 interrupt-parent = <&intc>;
29 interrupt-controller;
30 #interrupt-cells = <2>;
32 ab8500_clock: clock-controller {
33 compatible = "stericsson,ab8500-clk";
[all …]
Dberlin2cd.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500-mini (BG2CD) SoC";
17 #address-cells = <1>;
18 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a9";
[all …]
Dvf610-zii-cfu1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
15 stdout-path = &uart0;
20 reg = <0x80000000 0x20000000>;
23 gpio-leds {
24 compatible = "gpio-leds";
25 pinctrl-0 = <&pinctrl_leds_debug>;
26 pinctrl-names = "default";
28 led-debug {
31 linux,default-trigger = "heartbeat";
[all …]
Dimx6qdl-gw5904.dtsi4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include <dt-bindings/gpio/gpio.h>
49 #include <dt-bindings/input/linux-event-codes.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
63 stdout-path = &uart2;
67 compatible = "pwm-backlight";
69 brightness-levels = <0 4 8 16 32 64 128 255>;
70 default-brightness-level = <7>;
73 gpio-keys {
[all …]
/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
35 #address-cells = <1>;
36 #size-cells = <0>;
40 compatible = "arm,cortex-a72";
[all …]
/linux-5.10/Documentation/devicetree/bindings/bus/
Dbaikal,bt1-axi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
23 accessible by means of the Baikal-T1 System Controller.
26 - $ref: /schemas/simple-bus.yaml#
[all …]
/linux-5.10/Documentation/devicetree/bindings/i2c/
Dbrcm,brcmstb-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/brcm,brcmstb-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kamal Dasu <kdasu.kdev@gmail.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - brcm,bcm2711-hdmi-i2c
19 - brcm,brcmstb-i2c
20 - brcm,brcmper-i2c
22 reg:
[all …]
/linux-5.10/arch/arm64/boot/dts/renesas/
Dbeacon-renesom-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/gpio/gpio.h>
12 reg = <0x0 0x48000000 0x0 0x78000000>;
17 reg = <0x6 0x00000000 0x0 0x80000000>;
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <32768>;
24 clock-output-names = "osc_32k";
28 compatible = "regulator-fixed";
29 regulator-name = "fixed-1.8V";
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/
Dallwinner,sun8i-r40-tcon-top.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
22 / [0] TCON-LCD0
25 \ / [1] TCON-LCD1 - LCD1/LVDS1
26 TCON-TOP
27 / \ [2] TCON-TV0 [0] - TVE0/RGB
[all …]
/linux-5.10/Documentation/devicetree/bindings/soc/mediatek/
Dpwrap.txt20 - compatible:
21 "mediatek,mt2701-pwrap" for MT2701/7623 SoCs
22 "mediatek,mt6765-pwrap" for MT6765 SoCs
23 "mediatek,mt6779-pwrap" for MT6779 SoCs
24 "mediatek,mt6797-pwrap" for MT6797 SoCs
25 "mediatek,mt7622-pwrap" for MT7622 SoCs
26 "mediatek,mt8135-pwrap" for MT8135 SoCs
27 "mediatek,mt8173-pwrap" for MT8173 SoCs
28 "mediatek,mt8183-pwrap" for MT8183 SoCs
29 "mediatek,mt8516-pwrap" for MT8516 SoCs
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/ti/
Dti,omap5-dss.txt4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,omap5-dss"
12 - reg: address and length of the register space
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
18 - DISPC
21 - DSS Submodules: RFBI, DSI, HDMI
22 - Video port for DPI output
[all …]
/linux-5.10/Documentation/devicetree/bindings/spi/
Datmel-quadspi.txt4 - compatible: Should be one of the following:
5 - "atmel,sama5d2-qspi"
6 - "microchip,sam9x60-qspi"
7 - reg: Should contain the locations and lengths of the base registers
9 - reg-names: Should contain the resource reg names:
10 - qspi_base: configuration register address space
11 - qspi_mmap: memory mapped address space
12 - interrupts: Should contain the interrupt for the device.
13 - clocks: Should reference the peripheral clock and the QSPI system
15 - clock-names: Should contain "pclk" for the peripheral clock and "qspick"
[all …]
/linux-5.10/Documentation/devicetree/bindings/thermal/
Dnvidia,tegra124-soctherm.txt4 or interrupt-based thermal monitoring, CPU and GPU throttling based
10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11 For Tegra132, must contain "nvidia,tegra132-soctherm".
12 For Tegra210, must contain "nvidia,tegra210-soctherm".
13 - reg : Should contain at least 2 entries for each entry in reg-names:
14 - SOCTHERM register set
15 - Tegra CAR register set: Required for Tegra124 and Tegra210.
16 - CCROC register set: Required for Tegra132.
17 - reg-names : Should contain at least 2 entries:
18 - soctherm-reg
[all …]
/linux-5.10/Documentation/devicetree/bindings/mailbox/
Dti,message-manager.txt7 "proxies" - each instance is unidirectional and is instantiated at SoC
13 --------------------
14 - compatible: Shall be: "ti,k2g-message-manager"
15 - reg-names queue_proxy_region - Map the queue proxy region.
16 queue_state_debug_region - Map the queue state debug
18 - reg: Contains the register map per reg-names.
19 - #mbox-cells Shall be 2. Contains the queue ID and proxy ID in that
21 - interrupt-names: Contains interrupt names matching the rx transfer path
24 For ti,k2g-message-manager, this shall contain:
26 - interrupts: Contains the interrupt information corresponding to
[all …]
/linux-5.10/Documentation/devicetree/bindings/display/msm/
Dgpu.txt4 - compatible: "qcom,adreno-XYZ.W", "qcom,adreno" or
5 "amd,imageon-XYZ.W", "amd,imageon"
6 for example: "qcom,adreno-306.0", "qcom,adreno"
9 with the chip-id.
11 - reg: Physical base address and length of the controller's registers.
12 - interrupts: The interrupt signal from the gpu.
13 - clocks: device clocks (if applicable)
14 See ../clocks/clock-bindings.txt for details.
15 - clock-names: the following clocks are required by a3xx, a4xx and a5xx
22 - qcom,adreno-630.2
[all …]
Ddsi.txt5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
[all …]
/linux-5.10/Documentation/devicetree/bindings/phy/
Dallwinner,sun8i-h3-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-h3-usb-phy
20 reg:
22 - description: PHY Control registers
[all …]
/linux-5.10/Documentation/devicetree/bindings/arm/
Dcoresight.txt11 * Required properties for all components *except* non-configurable replicators
12 and non-configurable funnels:
16 - Embedded Trace Buffer (version 1.0):
17 "arm,coresight-etb10", "arm,primecell";
19 - Trace Port Interface Unit:
20 "arm,coresight-tpiu", "arm,primecell";
22 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
26 "arm,coresight-tmc", "arm,primecell";
28 - Trace Programmable Funnel:
29 "arm,coresight-dynamic-funnel", "arm,primecell";
[all …]
/linux-5.10/arch/mips/boot/dts/qca/
Dar9132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ath79-clk.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 #address-cells = <1>;
12 #size-cells = <0>;
18 reg = <0>;
22 cpuintc: interrupt-controller {
23 compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
25 interrupt-controller;
[all …]

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