| /linux-5.10/drivers/clk/sunxi/ |
| D | clk-sun4i-display.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
12 #include <linux/reset-controller.h>
33 void __iomem *reg; member
51 u32 reg; in sun4i_a10_display_assert() local
53 spin_lock_irqsave(data->lock, flags); in sun4i_a10_display_assert()
55 reg = readl(data->reg); in sun4i_a10_display_assert()
56 writel(reg & ~BIT(data->offset + id), data->reg); in sun4i_a10_display_assert()
58 spin_unlock_irqrestore(data->lock, flags); in sun4i_a10_display_assert()
[all …]
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| /linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | p4080si-pre.dtsi | 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
14 * names of its contributors may be used to endorse or promote products
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
91 #address-cells = <1>;
92 #size-cells = <0>;
96 reg = <0>;
98 next-level-cache = <&L2_0>;
[all …]
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| D | c293pcie.dts | 14 * names of its contributors may be used to endorse or promote products
35 /include/ "c293si-pre.dtsi"
46 reg = <0xf 0xffe1e000 0 0x2000>;
58 reg = <0xf 0xffe0a000 0 0x1000>;
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "cfi-flash";
78 reg = <0x0 0x0 0x4000000>;
79 bank-width = <2>;
80 device-width = <1>;
[all …]
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| D | pq3-etsec2-2.dtsi | 14 * names of its contributors may be used to endorse or promote products
36 #address-cells = <1>;
37 #size-cells = <0>;
38 compatible = "fsl,etsec2-tbi";
39 reg = <0x26000 0x1000 0xb1030 0x4>;
43 #address-cells = <1>;
44 #size-cells = <1>;
50 fsl,magic-packet;
51 local-mac-address = [ 00 00 00 00 00 00 ];
54 queue-group@b2000 {
[all …]
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| D | pq3-etsec2-0.dtsi | 14 * names of its contributors may be used to endorse or promote products
37 #address-cells = <1>;
38 #size-cells = <0>;
39 compatible = "fsl,etsec2-mdio";
40 reg = <0x24000 0x1000 0xb0030 0x4>;
44 #address-cells = <1>;
45 #size-cells = <1>;
51 fsl,magic-packet;
52 local-mac-address = [ 00 00 00 00 00 00 ];
55 queue-group@b0000 {
[all …]
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| D | pq3-etsec2-1.dtsi | 14 * names of its contributors may be used to endorse or promote products
37 #address-cells = <1>;
38 #size-cells = <0>;
39 compatible = "fsl,etsec2-tbi";
40 reg = <0x25000 0x1000 0xb1030 0x4>;
44 #address-cells = <1>;
45 #size-cells = <1>;
51 fsl,magic-packet;
52 local-mac-address = [ 00 00 00 00 00 00 ];
55 queue-group@b1000 {
[all …]
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| D | mpc8572si-pre.dtsi | 14 * names of its contributors may be used to endorse or promote products
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 #address-cells = <1>;
59 #size-cells = <0>;
63 reg = <0x0>;
64 next-level-cache = <&L2>;
69 reg = <0x1>;
[all …]
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| D | p1021si-pre.dtsi | 14 * names of its contributors may be used to endorse or promote products
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
56 #address-cells = <1>;
57 #size-cells = <0>;
61 reg = <0x0>;
62 next-level-cache = <&L2>;
67 reg = <0x1>;
[all …]
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| D | p1020si-pre.dtsi | 14 * names of its contributors may be used to endorse or promote products
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
56 #address-cells = <1>;
57 #size-cells = <0>;
61 reg = <0x0>;
62 next-level-cache = <&L2>;
67 reg = <0x1>;
[all …]
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| D | p2020si-pre.dtsi | 14 * names of its contributors may be used to endorse or promote products
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
57 #address-cells = <1>;
58 #size-cells = <0>;
62 reg = <0x0>;
63 next-level-cache = <&L2>;
68 reg = <0x1>;
[all …]
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| D | p1022si-pre.dtsi | 14 * names of its contributors may be used to endorse or promote products
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
58 #address-cells = <1>;
59 #size-cells = <0>;
63 reg = <0x0>;
64 next-level-cache = <&L2>;
69 reg = <0x1>;
[all …]
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| D | t4240si-pre.dtsi | 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
14 * names of its contributors may be used to endorse or promote products
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
87 #address-cells = <1>;
88 #size-cells = <0>;
92 reg = <0 1>;
94 next-level-cache = <&L2_1>;
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/regulator/ |
| D | tps65218.txt | 4 - compatible: "ti,tps65218"
5 - reg: I2C slave address
7 - List of regulators provided by this controller, must be named
8 after their hardware counterparts: dcdc[1-6] and ldo1
9 - This is the list of child nodes that specify the regulator
14 The valid names for regulators are:
15 tps65217: regulator-dcdc1, regulator-dcdc2, regulator-dcdc3, regulator-dcdc4,
16 regulator-dcdc5, regulator-dcdc6, regulator-ldo1, regulator-ls3.
21 reg = <0x24>;
24 interrupt-controller;
[all …]
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| /linux-5.10/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-pcie.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
7 compatible = "brcm,iproc-pcie-paxc-v2";
8 reg = <0 0x60400000 0 0x1000>;
9 linux,pci-domain = <8>;
11 bus-range = <0x0 0x1>;
13 #address-cells = <3>;
14 #size-cells = <2>;
18 dma-coherent;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/display/bridge/ |
| D | ite,it6505.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Allen Chen <allen.chen@ite.com.tw>
13 The IT6505 is a high-performance DisplayPort 1.1a transmitter,
16 and ensures robust transmission of high-quality uncompressed video
27 transmission of high-definition content. Users of the IT6505 need not
34 reg:
37 ovdd-supply:
41 pwr18-supply:
[all …]
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| /linux-5.10/arch/arm/boot/dts/ |
| D | at91sam9261ek.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board
5 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 /dts-v1/;
16 stdout-path = "serial0:115200n8";
20 reg = <0x20000000 0x4000000>;
25 clock-frequency = <32768>;
29 clock-frequency = <18432000>;
40 atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
44 bits-per-pixel = <16>;
[all …]
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| D | sama5d3xdm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3dm.dtsi - Device Tree file for SAMA5 display module
15 reg = <0x1b>;
16 interrupt-parent = <&pioE>;
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_qt1070_irq>;
20 wakeup-source;
25 atmel,adc-ts-wires = <4>;
26 atmel,adc-ts-pressure-threshold = <10000>;
|
| D | vf610m4-colibri.dts | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Device tree for Colibri VF61 Cortex-M4 support
8 /dts-v1/;
12 model = "VF610 Cortex-M4";
17 stdout-path = "serial2:115200";
22 reg = <0x8c000000 0x3000000>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart2>;
53 vf610-colibri {
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| D | exynos5.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <1>;
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | fujitsu,mb86s70-crg11.txt | 2 -----------------------------------
5 - compatible : Shall contain "fujitsu,mb86s70-crg11"
6 - #clock-cells : Shall be 3 {cntrlr domain port}
13 compatible = "fujitsu,mb86s70-crg11";
14 #clock-cells = <3>;
18 #mbox-cells = <1>;
20 reg = <0 0x2B1F0000 0x1000>;
21 interrupts = <0 36 4>, /* LP Non-Sec */
22 <0 35 4>, /* HP Non-Sec */
25 clock-names = "clk";
|
| /linux-5.10/Documentation/devicetree/bindings/watchdog/ |
| D | zii,rave-sp-wdt.txt | 7 Documentation/devicetree/bindings/mfd/zii,rave-sp.txt)
11 - compatible: Depending on wire protocol implemented by RAVE SP
13 - "zii,rave-sp-watchdog"
14 - "zii,rave-sp-watchdog-legacy"
18 - wdt-timeout: Two byte nvmem cell specified as per
23 rave-sp {
24 compatible = "zii,rave-sp-rdu1";
25 current-speed = <38400>;
28 wdt_timeout: wdt-timeout@8E {
29 reg = <0x8E 2>;
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | zx-dw-mshc.txt | 7 by synopsys-dw-mshc.txt and the properties used by the ZTE specific
13 - "zte,zx296718-dw-mshc": for ZX SoCs
18 compatible = "zte,zx296718-dw-mshc";
19 reg = <0x01110000 0x1000>;
21 fifo-depth = <32>;
22 data-addr = <0x200>;
23 fifo-watermark-aligned;
24 bus-width = <4>;
25 clock-frequency = <50000000>;
27 clock-names = "biu", "ciu";
[all …]
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| /linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | sdm660-xiaomi-lavender.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
19 stdout-path = "serial0:115200n8";
22 reserved-memory {
23 #address-cells = <2>;
24 #size-cells = <2>;
29 reg = <0x0 0xa0000000 0x0 0x400000>;
30 console-size = <0x20000>;
31 record-size = <0x20000>;
32 ftrace-size = <0x0>;
[all …]
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| /linux-5.10/drivers/clk/ti/ |
| D | clk.c | 6 * Tero Kristo <t-kristo@ti.com>
19 #include <linux/clk-provider.h>
48 static void clk_memmap_writel(u32 val, const struct clk_omap_reg *reg) in clk_memmap_writel() argument
50 struct clk_iomap *io = clk_memmaps[reg->index]; in clk_memmap_writel()
52 if (reg->ptr) in clk_memmap_writel()
53 writel_relaxed(val, reg->ptr); in clk_memmap_writel()
54 else if (io->regmap) in clk_memmap_writel()
55 regmap_write(io->regmap, reg->offset, val); in clk_memmap_writel()
57 writel_relaxed(val, io->mem + reg->offset); in clk_memmap_writel()
70 static void clk_memmap_rmw(u32 val, u32 mask, const struct clk_omap_reg *reg) in clk_memmap_rmw() argument
[all …]
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| /linux-5.10/arch/arm64/boot/dts/renesas/ |
| D | r8a77965-ulcb.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the M3NULCB (R-Car Starter Kit Pro) board
9 /dts-v1/;
20 reg = <0x0 0x48000000 0x0 0x78000000>;
31 clock-names = "du.0", "du.1", "du.3",
|