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/linux-5.10/arch/powerpc/boot/dts/fsl/
Dt1042d4rdb.dts14 * names of its contributors may be used to endorse or promote products
35 /include/ "t104xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
47 compatible = "fsl,t1040d4rdb-cpld",
48 "fsl,deepsleep-cpld";
55 phy-handle = <&phy_sgmii_0>;
56 phy-connection-type = "sgmii";
60 phy-handle = <&phy_sgmii_1>;
[all …]
Dbsc9132qds.dtsi2 * BSC9132 QDS Device Tree Source stub (no addresses or top-level ranges)
14 * names of its contributors may be used to endorse or promote products
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
46 #address-cells = <1>;
47 #size-cells = <1>;
[all …]
Dpq3-mpic.dtsi14 * names of its contributors may be used to endorse or promote products
36 interrupt-controller;
37 #address-cells = <0>;
38 #interrupt-cells = <4>;
39 reg = <0x40000 0x40000>;
41 device_type = "open-pic";
42 big-endian;
43 single-cpu-affinity;
44 last-interrupt-source = <255>;
48 compatible = "fsl,mpic-global-timer";
[all …]
/linux-5.10/arch/arm/boot/dts/
Domap3-evm-processor-common.dtsi8 reg = <0x80000000 0x10000000>; /* 256 MB */
12 pinctrl-names = "default";
13 pinctrl-0 = <&wl12xx_gpio>;
18 vdds_dsi-supply = <&vpll2>;
19 vdda_video-supply = <&lcd_3v3>;
20 pinctrl-names = "default";
21 pinctrl-0 = <
28 pinctrl-names = "default";
29 pinctrl-0 = <&ehci_phy_pins>;
33 pinctrl-names = "default";
[all …]
Dsun8i-h3-beelink-x2.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun8i-h3.dtsi"
45 #include "sunxi-common-regulators.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
48 #include <dt-bindings/input/input.h>
52 compatible = "roofull,beelink-x2", "allwinner,sun8i-h3";
61 stdout-path = "serial0:115200n8";
65 compatible = "hdmi-connector";
70 remote-endpoint = <&hdmi_out_con>;
[all …]
Dsun8i-h3-orangepi-pc.dts2 * Copyright (C) 2015 Chen-Yu Tsai <wens@csie.org>
4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun8i-h3.dtsi"
45 #include "sunxi-common-regulators.dtsi"
47 #include <dt-bindings/gpio/gpio.h>
48 #include <dt-bindings/input/input.h>
52 compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
60 stdout-path = "serial0:115200n8";
64 compatible = "hdmi-connector";
[all …]
Dgr-peach-audiocamerashield.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the GR-Peach audiocamera shield expansion board
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
13 /* On-board camera clock. */
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <27000000>;
28 /* CEU pins: VIO_D[0-10], VIO_VD, VIO_HD, VIO_CLK */
44 pinctrl-names = "default";
[all …]
Domap3-evm-37xx.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/
5 /dts-v1/;
8 #include "omap3-evm-common.dtsi"
9 #include "omap3-evm-processor-common.dtsi"
13 compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3";
17 pinctrl-names = "default";
18 pinctrl-0 = <&hsusb2_2_pins>;
21 pinctrl-single,pins = <
33 pinctrl-single,pins = <
[all …]
Darmada-xp-db-dxbc2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for DB-DXBC2 board
7 * Based on armada-xp-db.dts
12 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
19 /dts-v1/;
20 #include "armada-xp-98dx4251.dtsi"
24 compatible = "marvell,db-dxbc2", "marvell,armadaxp-98dx4251", "marvell,armada-370-xp";
32 reg = <0 0x00000000 0 0x20000000>; /* 512 MB */
43 devbus,bus-width = <16>;
44 devbus,turn-off-ps = <60000>;
[all …]
Dexynos4412-itop-scp-core.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
17 #include "exynos4412-ppmu-common.dtsi"
18 #include "exynos-mfc-reserved-memory.dtsi"
23 reg = <0x40000000 0x40000000>;
27 compatible = "samsung,secure-firmware";
28 reg = <0x0203F000 0x1000>;
31 fixed-rate-clocks {
[all …]
Dsun8i-q8-common.dtsi4 * This file is dual-licensed: you can use it either under the terms
42 #include "sunxi-reference-design-tablet.dtsi"
43 #include "sun8i-reference-design-tablet.dtsi"
48 /* Make u-boot set mac-address for wifi without an eeprom */
55 enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
56 power-supply = <&reg_dc1sw>;
60 remote-endpoint = <&tcon0_out_lcd>;
66 compatible = "mmc-pwrseq-simple";
68 * Q8 boards use various PL# pins as wifi-en. On other boards
70 * short-circuits we configure these as inputs with pull-ups via
[all …]
Dkirkwood-dns325.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "kirkwood-dnskw.dtsi"
7 model = "D-Link DNS-325 NAS (Rev A1)";
8 …compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281"…
12 reg = <0x00000000 0x10000000>;
17 stdout-path = &uart0;
20 gpio-leds {
21 compatible = "gpio-leds";
22 pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325
[all …]
/linux-5.10/drivers/clk/sunxi/
Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
19 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
23 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
24 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
25 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
40 * driver then responds by auto-reparenting the clock.
57 const char *clk_name = node->name; in sun7i_a20_gmac_clk_setup()
[all …]
/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3399-puma-haikou.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "rk3399-puma.dtsi"
10 model = "Theobroma Systems RK3399-Q7 SoM";
11 compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399";
14 stdout-path = "serial0:115200n8";
18 pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
20 sd_card_led: led-1 {
23 linux,default-trigger = "mmc0";
27 i2s0-sound {
[all …]
/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dmicrochip,pic32-pinctrl.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
12 - compatible: "microchip,pic32mada-pinctrl"
13 - reg: Address range of the pinctrl registers.
14 - clocks: Clock specifier (see clock bindings for details)
16 Required properties for pin configuration sub-nodes:
17 - pins: List of pins to which the configuration applies.
19 Optional properties for pin configuration sub-nodes:
20 ----------------------------------------------------
21 - function: Mux function for the specified pins.
[all …]
/linux-5.10/Documentation/devicetree/bindings/clock/
Dimx25-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx25-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
18 --------------------------
152 const: fsl,imx25-ccm
154 reg:
160 '#clock-cells':
164 - compatible
[all …]
/linux-5.10/Documentation/devicetree/bindings/regulator/
Drichtek,rt4801-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rt4801-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
18 https://www.richtek.com/assets/product_file/RT4801H/DS4801H-00.pdf
20 #The valid names for RT4801 regulator nodes are:
26 - richtek,rt4801
28 reg:
31 enable-gpios:
[all …]
Dtps65132-regulator.txt4 - compatible: "ti,tps65132"
5 - reg: I2C slave address
9 device node describe the properties of these regulators. The sub-node
10 names must be as follows:
11 -For regulator outp, the sub node name should be "outp".
12 -For regulator outn, the sub node name should be "outn".
14 -enable-gpios:(active high, output) Regulators are controlled by the input pins.
17 -active-discharge-gpios: (active high, output) Some configurations use delay mechanisms
20 the delay mechanism. Requires specification of ti,active-discharge-time-us
21 -ti,active-discharge-time-us: how long the active discharge gpio should be
[all …]
/linux-5.10/drivers/clk/mvebu/
Darmada-37xx-xtal.c1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <linux/clk-provider.h>
21 struct device_node *np = pdev->dev.of_node; in armada_3700_xtal_clock_probe()
27 u32 reg; in armada_3700_xtal_clock_probe() local
30 xtal_hw = devm_kzalloc(&pdev->dev, sizeof(*xtal_hw), GFP_KERNEL); in armada_3700_xtal_clock_probe()
32 return -ENOMEM; in armada_3700_xtal_clock_probe()
36 parent = np->parent; in armada_3700_xtal_clock_probe()
38 dev_err(&pdev->dev, "no parent\n"); in armada_3700_xtal_clock_probe()
39 return -ENODEV; in armada_3700_xtal_clock_probe()
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dingenic,nemc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
14 pattern: "^memory-controller@[0-9a-f]+$"
18 - enum:
19 - ingenic,jz4740-nemc
20 - ingenic,jz4780-nemc
21 - items:
[all …]
/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls1028a-kontron-sl28-var3-ads2.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board on a SMARC Eval 2.0
10 /dts-v1/;
11 #include "fsl-ls1028a-kontron-sl28.dts"
14 model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";
15 compatible = "kontron,sl28-var3-ads2", "kontron,sl28-var3",
18 pwm-fan {
19 compatible = "pwm-fan";
20 cooling-min-state = <0>;
21 cooling-max-state = <3>;
[all …]
/linux-5.10/drivers/clk/versatile/
Dclk-vexpress-osc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
17 struct regmap *reg; member
31 regmap_read(osc->reg, 0, &rate); in vexpress_osc_recalc_rate()
41 if (osc->rate_min && rate < osc->rate_min) in vexpress_osc_round_rate()
42 rate = osc->rate_min; in vexpress_osc_round_rate()
44 if (osc->rate_max && rate > osc->rate_max) in vexpress_osc_round_rate()
45 rate = osc->rate_max; in vexpress_osc_round_rate()
55 return regmap_write(osc->reg, 0, rate); in vexpress_osc_set_rate()
72 osc = devm_kzalloc(&pdev->dev, sizeof(*osc), GFP_KERNEL); in vexpress_osc_probe()
[all …]
/linux-5.10/drivers/macintosh/
Dwindfarm_smu_controls.c1 // SPDX-License-Identifier: GPL-2.0-only
46 u32 reg; /* index in SMU */ member
77 return -EINVAL; in smu_set_fan()
119 if (value < fct->min) in smu_fan_set()
120 value = fct->min; in smu_fan_set()
121 if (value > fct->max) in smu_fan_set()
122 value = fct->max; in smu_fan_set()
123 fct->value = value; in smu_fan_set()
125 return smu_set_fan(fct->fan_type, fct->reg, value); in smu_fan_set()
131 *value = fct->value; /* todo: read from SMU */ in smu_fan_get()
[all …]
/linux-5.10/Documentation/devicetree/bindings/input/
Delan_i2c.txt4 - compatible: must be "elan,ekth3000".
5 - reg: I2C address of the chip.
6 - interrupts: interrupt to which the chip is connected (see interrupt
10 - wakeup-source: touchpad can be used as a wakeup source.
11 - pinctrl-names: should be "default" (see pinctrl binding [1]).
12 - pinctrl-0: a phandle pointing to the pin settings for the device (see
14 - vcc-supply: a phandle for the regulator supplying 3.3V power.
15 - elan,trackpoint: touchpad can support a trackpoint (boolean)
16 - elan,clickpad: touchpad is a clickpad (the entire surface is a button)
17 - elan,middle-button: touchpad has a physical middle button
[all …]
/linux-5.10/Documentation/devicetree/bindings/hwmon/
Dltc2978.txt4 - compatible: should contain one of:
29 - reg: I2C slave address
32 - regulators: A node that houses a sub-node for each regulator controlled by
33 the device. Each sub-node is identified using the node's name, with valid
34 values listed below. The content of each sub-node is defined by the
37 Valid names of regulators depend on number of supplies supported per device:
38 * ltc2972 vout0 - vout1
39 * ltc2974, ltc2975 : vout0 - vout3
40 * ltc2977, ltc2979, ltc2980, ltm2987 : vout0 - vout7
41 * ltc2978 : vout0 - vout7
[all …]

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