| /linux-6.15/Documentation/devicetree/bindings/dma/ |
| D | fsl-qdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Layerscape SoC qDMA Controller
10 - Frank Li <Frank.Li@nxp.com>
15 - const: fsl,ls1021a-qdma
16 - items:
17 - enum:
18 - fsl,ls1028a-qdma
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| /linux-6.15/Documentation/devicetree/bindings/net/ |
| D | airoha,en7581-eth.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/airoha,en7581-eth.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
14 These SoCs have multi-GMAC ports.
19 - airoha,en7581-eth
23 - description: Frame engine base address
24 - description: QDMA0 base address
25 - description: QDMA1 base address
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| /linux-6.15/drivers/dma/ |
| D | fsl-qdma.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright 2014-2015 Freescale
18 #include <linux/dma-mapping.h>
21 #include "virt-dma.h"
137 (((fsl_qdma_engine)->block_offset) * (x))
140 * struct fsl_qdma_format - This is the struct holding describing compound
141 * descriptor format with qDMA.
145 * 32-bits address in memory 40-bit address.
146 * @addr_hi: Same as above member, but point high 8-bits in
147 * memory 40-bit address.
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| /linux-6.15/drivers/net/ethernet/airoha/ |
| D | airoha_eth.c | 1 // SPDX-License-Identifier: GPL-2.0-only
37 static void airoha_qdma_set_irqmask(struct airoha_qdma *qdma, int index, in airoha_qdma_set_irqmask() argument
42 if (WARN_ON_ONCE(index >= ARRAY_SIZE(qdma->irqmask))) in airoha_qdma_set_irqmask()
45 spin_lock_irqsave(&qdma->irq_lock, flags); in airoha_qdma_set_irqmask()
47 qdma->irqmask[index] &= ~clear; in airoha_qdma_set_irqmask()
48 qdma->irqmask[index] |= set; in airoha_qdma_set_irqmask()
49 airoha_qdma_wr(qdma, REG_INT_ENABLE(index), qdma->irqmask[index]); in airoha_qdma_set_irqmask()
53 airoha_qdma_rr(qdma, REG_INT_ENABLE(index)); in airoha_qdma_set_irqmask()
55 spin_unlock_irqrestore(&qdma->irq_lock, flags); in airoha_qdma_set_irqmask()
58 static void airoha_qdma_irq_enable(struct airoha_qdma *qdma, int index, in airoha_qdma_irq_enable() argument
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| /linux-6.15/drivers/pci/controller/ |
| D | pcie-xilinx-dma-pl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "pcie-xilinx-common.h"
61 /* Root Port Error Register definitions */
81 QDMA, enumerator
85 * struct xilinx_pl_dma_variant - PL DMA PCIe variant information
102 * struct pl_dma_pcie - PCIe port information
113 * @intx_irq: INTx error interrupt number
135 if (port->variant->version == QDMA) in pcie_read()
136 return readl(port->reg_base + reg + QDMA_BRIDGE_BASE_OFF); in pcie_read()
138 return readl(port->reg_base + reg); in pcie_read()
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| /linux-6.15/drivers/crypto/hisilicon/ |
| D | qm.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/dma-mapping.h>
57 #define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1)
65 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
68 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
258 ((((u32)cq_depth) - 1) | ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
272 ((((u32)sq_depth) - 1) | ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
388 * struct qm_hw_err - Structure describing the device errors
389 * @list: hardware error list
390 * @timestamp: timestamp when the error occurred
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| /linux-6.15/drivers/dma/fsl-dpaa2-qdma/ |
| D | dpaa2-qdma.c | 1 // SPDX-License-Identifier: GPL-2.0
11 #include <soc/fsl/dpaa2-io.h>
13 #include "../virt-dma.h"
15 #include "dpaa2-qdma.h"
32 struct dpaa2_qdma_engine *dpaa2_qdma = dpaa2_chan->qdma; in dpaa2_qdma_alloc_chan_resources()
33 struct device *dev = &dpaa2_qdma->priv->dpdmai_dev->dev; in dpaa2_qdma_alloc_chan_resources()
35 dpaa2_chan->fd_pool = dma_pool_create("fd_pool", dev, in dpaa2_qdma_alloc_chan_resources()
38 if (!dpaa2_chan->fd_pool) in dpaa2_qdma_alloc_chan_resources()
41 dpaa2_chan->fl_pool = in dpaa2_qdma_alloc_chan_resources()
46 if (!dpaa2_chan->fl_pool) in dpaa2_qdma_alloc_chan_resources()
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| D | dpdmai.c | 1 // SPDX-License-Identifier: GPL-2.0
57 * dpdmai_open() - Open a control session for the specified object
71 * Return: '0' on Success; Error code otherwise.
85 cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id); in dpdmai_open()
100 * dpdmai_close() - Close the control session of the object
108 * Return: '0' on Success; Error code otherwise.
124 * dpdmai_destroy() - Destroy the DPDMAI object and release all its resources.
130 * Return: '0' on Success; error code otherwise.
142 cmd_params->dpdmai_id = cpu_to_le32(dpdmai_id); in dpdmai_destroy()
150 * dpdmai_enable() - Enable the DPDMAI, allow sending and receiving frames.
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| /linux-6.15/drivers/dma/amd/qdma/ |
| D | qdma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for AMD Queue-based DMA Subsystem
5 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
10 #include <linux/dma-mapping.h>
17 #include "qdma.h"
19 #define CHAN_STR(q) (((q)->dir == DMA_MEM_TO_DEV) ? "H2C" : "C2H")
20 #define QDMA_REG_OFF(d, r) ((d)->roffs[r].off)
22 /* MMIO regmap config for all QDMA registers */
43 idx = qdev->qintr_rings[qdev->qintr_ring_idx++].ridx; in qdma_get_intr_ring_idx()
44 qdev->qintr_ring_idx %= qdev->qintr_ring_num; in qdma_get_intr_ring_idx()
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| /linux-6.15/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1043a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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| D | fsl-ls1046a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
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| D | fsl-ls1028a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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| /linux-6.15/drivers/net/ethernet/mediatek/ |
| D | mtk_eth_soc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
60 .qdma = {
126 .qdma = {
177 .qdma = {
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| /linux-6.15/include/linux/ |
| D | hisi_acc_qm.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
327 * @isolate_lock: protects device error log
328 * @err_threshold: user config error threshold which triggers isolation
330 * @uacce_hw_errs: index into qm device error list
374 struct qm_dma qdma; member
446 struct qm_dma qdma; member
471 return -EINVAL; in vfs_num_set()
478 return -EINVAL; in vfs_num_set()
489 return -EINVAL; in mode_set()
494 return -EINVAL; in mode_set()
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| /linux-6.15/arch/arm/boot/dts/nxp/ls/ |
| D | ls1021a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
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| /linux-6.15/drivers/usb/mtu3/ |
| D | mtu3_qmu.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * mtu3_qmu.c - Queue Management Unit driver for device controller
34 #define GET_GPD_HWO(gpd) (le32_to_cpu((gpd)->dw0_info) & GPD_FLAGS_HWO)
41 ((mtu)->gen2cp) ? GPD_RX_BUF_LEN_EL(x_) : GPD_RX_BUF_LEN_OG(x_); \
49 ((mtu)->gen2cp) ? GPD_DATA_LEN_EL(x_) : GPD_DATA_LEN_OG(x_); \
60 ((mtu)->gen2cp) ? GPD_EXT_NGP_EL(x_) : GPD_EXT_NGP_OG(x_); \
66 ((mtu)->gen2cp) ? GPD_EXT_BUF_EL(x_) : GPD_EXT_BUF_OG(x_); \
122 dma_addr_t dma_base = ring->dma; in gpd_dma_to_virt()
123 struct qmu_gpd *gpd_head = ring->start; in gpd_dma_to_virt()
124 u32 offset = (dma_addr - dma_base) / sizeof(*gpd_head); in gpd_dma_to_virt()
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| /linux-6.15/include/uapi/linux/ |
| D | hdreg.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
17 #define IDE_DRIVE_TASK_INVALID -1
137 * 0x01->0x02 Reserved
139 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
141 * 0x04->0x07 Reserved
146 * 0x09->0x0F Reserved
151 * 0x10->0x1F Reserved
153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
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| /linux-6.15/drivers/net/ethernet/sfc/siena/ |
| D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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| /linux-6.15/drivers/net/ethernet/sfc/ |
| D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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| /linux-6.15/ |
| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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