Searched full:pulse (Results 1 – 25 of 33) sorted by relevance
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| /qemu/rust/qemu-api/src/ |
| H A D | irq.rs | 65 /// Send a high-low pulse to the interrupt sink.
66 pub fn pulse(&self) { in pulse() method
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| /qemu/hw/sensor/ |
| H A D | max31785.c | 75 #define MAX31785_FAN_CONFIG_PULSE(pulse) (pulse << 4) argument
76 #define MAX31785_DEFAULT_FAN_CONFIG_1_2(pulse) \ argument
77 (MAX31785_FAN_CONFIG_ENABLE | MAX31785_FAN_CONFIG_PULSE(pulse))
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| /qemu/audio/ |
| H A D | meson.build | 17 ['pa', pulse, files('paaudio.c')],
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| H A D | paaudio.c | 8 #include <pulse/pulseaudio.h>
840 snprintf(pidfile, sizeof(pidfile), "%s/pulse/pid", runtime); in qpa_audio_init()
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| /qemu/docs/system/arm/ |
| H A D | raspi.rst | 43 * Pulse Width Modulation (PWM)
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| H A D | nuvoton.rst | 54 * Pulse Width Modulation (PWM)
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| /qemu/docs/system/devices/ |
| H A D | virtio-snd.rst | 36 or ``-audio driver=pa,model=virtio,server=/run/user/1000/pulse/native``
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| /qemu/include/hw/misc/ |
| H A D | npcm7xx_pwm.h | 75 * struct NPCM7xxPWMState - Pulse Width Modulation device state.
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| H A D | bcm2835_cprman_internals.h | 697 .name = "pulse",
698 FILL_CLOCK_MUX_INIT_INFO(PULSE, xosc),
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| /qemu/target/ppc/ |
| H A D | timebase_helper.c | 241 * | 6 SYNC_WAIT | "sync pulse from ChipTOD" | 7 |
402 * mtspr always clears this. The sync pulse timer makes it come back in helper_store_tfmr()
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| /qemu/hw/input/ |
| H A D | pckbd.c | 79 /* Pulse bits 3-0 of the output port P2. */
81 /* Pulse bit 0 of the output port P2 = CPU reset. */
83 /* Pulse no bits of the output port P2. */
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| /qemu/tests/qtest/ |
| H A D | dm163-test.c | 138 /* Pulse one more bit in the bank, check that we get a one */ in test_dm163_bank()
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| H A D | fdc-test.c | 302 /* Insert media in drive. DSKCHK should not be reset until a step pulse in test_media_insert()
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| /qemu/hw/i2c/ |
| H A D | bitbang_i2c.c | 113 /* State is set/read at the start of the clock pulse. in bitbang_i2c_set()
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| /qemu/hw/arm/ |
| H A D | smmuv3.c | 44 * smmuv3_trigger_irq - pulse @irq if enabled and update
54 bool pulse = false; in smmuv3_trigger_irq() local
58 pulse = smmuv3_eventq_irq_enabled(s); in smmuv3_trigger_irq()
64 pulse = true; in smmuv3_trigger_irq()
78 pulse = smmuv3_gerror_irq_enabled(s); in smmuv3_trigger_irq()
82 if (pulse) { in smmuv3_trigger_irq()
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| /qemu/hw/block/ |
| H A D | trace-events | 8 fdctrl_tc_pulse(int level) "TC pulse: %u"
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| /qemu/hw/misc/ |
| H A D | slavio_misc.c | 224 // Send a pulse to floppy terminal count line in slavio_aux1_mem_writeb()
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| H A D | trace-events | 167 stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
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| /qemu/hw/intc/ |
| H A D | xlnx-zynqmp-ipi.c | 189 /* TRIG generates a pulse on the outbound signals. We use the in xlnx_zynqmp_ipi_trig_postw()
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| /qemu/hw/timer/ |
| H A D | exynos4210_pwm.c | 2 * Samsung exynos4210 Pulse Width Modulation Timer
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| H A D | aspeed_timer.c | 349 "%s: Timer does not support pulse mode\n", __func__); in aspeed_timer_ctrl_pulse_enable()
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| /qemu/hw/display/ |
| H A D | g364fb.c | 390 case 0x00128: /* Frame timing: broad pulse */ in g364fb_ctrl_write()
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| /qemu/hw/char/ |
| H A D | stm32l4x5_usart.c | 73 FIELD(CR2, LBCL, 8, 1) /* Last bit clock pulse */
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| /qemu/hw/net/ |
| H A D | ne2000.c | 584 /* nothing to do (end of reset pulse) */ in ne2000_reset_ioport_write()
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| /qemu/linux-user/ |
| H A D | syscall_defs.h | 288 abi_long ppsfreq; /* PPS (pulse per second) frequency */
318 abi_llong ppsfreq; /* PPS (pulse per second) frequency */
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