| /qemu/linux-user/loongarch64/ |
| H A D | target_syscall.h | 17 /* Saved main processor registers. */
|
| /qemu/linux-user/hppa/ |
| H A D | target_mman.h | 27 /* arch/parisc/include/asm/processor.h: DEFAULT_MAP_BASE32 */
|
| H A D | target_proc.h | 15 dprintf(fd, "processor\t: %d\n", i); in open_cpuinfo()
|
| /qemu/docs/system/i386/ |
| H A D | amd-memory-encryption.rst | 14 Key management for this feature is handled by a separate processor known as the
15 AMD secure processor (AMD-SP), which is present in AMD SOCs. Firmware running
258 …<https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.…
268 <https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.p…
|
| H A D | hyperv.rst | 57 processor index information. This enlightenment makes sense in conjunction with
59 Virtual Processor indices (e.g. when VP index needs to be passed in a
64 virtual processor run time in 100ns units. This gives guest operating system an
|
| /qemu/hw/s390x/ |
| H A D | ap-device.c | 2 * Adjunct Processor (AP) matrix device
|
| /qemu/target/xtensa/core-test_kc705_be/ |
| H A D | core-isa.h | 3 * processor CORE configuration
8 /* Xtensa processor core configuration information.
83 #define XCHAL_HAVE_PRID 1 /* processor ID register */
178 Processor Generator */
406 * These macros describe how Xtensa processor interrupt numbers
410 * See the Xtensa processor databook for more details.
|
| /qemu/include/ |
| H A D | elf.h | 113 uint8_t cpr1_size; /* The size of co-processor 1 registers */
114 uint8_t cpr2_size; /* The size of co-processor 2 registers */
116 uint32_t isa_ext; /* Mask of processor-specific extensions */
166 #define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */
202 #define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */
744 /* Processor specific flags for the ELF header e_flags field. */
792 /* Processor specific flags for the ELF header e_flags field. */
1279 /* Processor specific flags for the Ehdr e_flags field. */
1284 /* Processor specific values for the Phdr p_type field. */
1288 /* Processor specific flags for the Phdr p_flags field. */
[all …]
|
| /qemu/include/hw/i386/ |
| H A D | topology.h | 30 * Intel® 64 Architecture Processor Topology Enumeration
31 * http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/
|
| /qemu/hw/loongarch/ |
| H A D | virt-acpi-build.c | 58 /* Rev 1.0b, Table 5-13 Processor Local APIC Structure */ in virt_madt_cpu_entry()
61 build_append_int_noprefix(entry, uid, 1); /* ACPI Processor ID */ in virt_madt_cpu_entry()
142 /* Processor Core Interrupt Controller Structure */ in build_madt()
148 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor ID */ in build_madt()
203 /* Processor Local APIC/SAPIC Affinity Structure */ in build_srat()
|
| /qemu/linux-user/include/host/arm/ |
| H A D | host-signal.h | 36 * later processor. On v5 we will always report in host_signal_write()
|
| /qemu/linux-user/riscv/ |
| H A D | target_proc.h | 25 dprintf(fd, "processor\t: %d\n", i); in open_cpuinfo()
|
| /qemu/target/mips/ |
| H A D | internal.h | 57 * pipeline clock of the processor, not the issue width of the processor.
289 /* Check if the virtual processor is disabled due to a DVP */ in mips_vp_active()
|
| /qemu/target/xtensa/core-de212/ |
| H A D | core-isa.h | 3 * processor CORE configuration
8 /* Xtensa processor core configuration information.
84 #define XCHAL_HAVE_PRID 1 /* processor ID register */
187 Processor Generator */
440 * These macros describe how Xtensa processor interrupt numbers
444 * See the Xtensa processor databook for more details.
|
| /qemu/include/hw/intc/ |
| H A D | xlnx-zynqmp-ipi.h | 2 * QEMU model of the IPI Inter Processor Interrupt block
|
| /qemu/target/alpha/ |
| H A D | cpu.h | 218 /* Mask of PALmode, Processor State et al. Most of this gets copied
222 /* The high 32-bits of the processor cycle counter. */
360 /* Processor status constants. */
|
| /qemu/target/xtensa/core-sample_controller/ |
| H A D | core-isa.h | 3 * processor CORE configuration
8 /* Xtensa processor core configuration information.
84 #define XCHAL_HAVE_PRID 1 /* processor ID register */
201 Processor Generator */
461 * These macros describe how Xtensa processor interrupt numbers
465 * See the Xtensa processor databook for more details.
|
| /qemu/tests/functional/ |
| H A D | test_loongarch64_virt.py | 59 'processor : 3')
|
| /qemu/target/loongarch/ |
| H A D | README | 3 LoongArch is the general processor architecture of Loongson.
|
| /qemu/hw/smbios/ |
| H A D | smbios.c | 322 .name = "processor-family",
324 .help = "processor family",
326 .name = "processor-id",
328 .help = "processor id",
687 t->processor_family = 0xfe; /* use Processor Family 2 field */ in smbios_build_type_4_table()
725 error_setg(errp, "SMBIOS 2.0 doesn't support number of processor " in smbios_build_type_4_table()
1465 "processor-family", in smbios_entry_add()
1473 type4.processor_id = qemu_opt_get_number(opts, "processor-id", 0); in smbios_entry_add()
|
| /qemu/hw/arm/ |
| H A D | omap_sx1.c | 44 /* - ARM OMAP310 processor
57 /* - ARM OMAP310 processor
|
| /qemu/include/hw/arm/ |
| H A D | msf2-soc.h | 45 * the Cortex-M3 processor
|
| /qemu/target/i386/nvmm/ |
| H A D | nvmm-all.c | 192 error_report("NVMM: Failed to set virtual processor context," in nvmm_set_registers()
240 error_report("NVMM: Failed to get virtual processor context," in nvmm_get_registers()
755 error_report("NVMM: Failed to exec a virtual processor," in nvmm_vcpu_loop()
941 error_report("NVMM: Failed to create a virtual processor," in nvmm_init_vcpu()
955 error_report("NVMM: Failed to configure a virtual processor," in nvmm_init_vcpu()
965 error_report("NVMM: Failed to configure a virtual processor," in nvmm_init_vcpu()
977 error_report("NVMM: Failed to configure a virtual processor," in nvmm_init_vcpu()
|
| /qemu/target/xtensa/core-de233_fpu/ |
| H A D | core-isa.h | 3 * processor CORE configuration
8 /* Xtensa processor core configuration information.
84 #define XCHAL_HAVE_PRID 1 /* processor ID register */
243 Processor Generator */
530 * These macros describe how Xtensa processor interrupt numbers
534 * See the Xtensa processor databook for more details.
|
| /qemu/target/i386/ |
| H A D | cpu-internal.h | 30 /* feature flags names are taken from "Intel Processor Identification and
|