Searched full:processor (Results 176 – 200 of 262) sorted by relevance
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9 bswap32s(&ehdr->e_flags); /* Processor-specific flags */
91 case 0x4: /*processor clock frequency, Hz*/ in xtfpga_fpga_read()
473 /* LE: LSB transmitted first (default for ibex processor) */ in ibex_spi_host_write()
657 /* Virtual Processor Home Node */ in spapr_numa_register_types()
2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
1263 * the first supported Power Processor Mode in h_guest_set_capabilities()1268 /* set R5 to the first supported Power Processor Mode */ in h_guest_set_capabilities()
958 * processor GA series
43 /* the TR register is usable after processor reset despite in hvf_set_segment()
3 * parameters (CHAL) of the Xtensa processor core configuration.8 * In the Xtensa processor products released to date, all parameters
270 /* Processor identification */ in register_604_sprs()587 /* Processor identification */ in register_74xx_sprs()1059 /* Processor control */ in register_440_sprs()1074 /* Processor identification */ in register_440_sprs()2851 /* Processor identification */ in init_proc_e500()5462 /* Processor identification */ in register_book3s_ids_sprs()6423 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings6588 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings7425 * a processor attribute of some sort. in ppc_cpu_instance_init()
460 /* Processor control */ in register_generic_sprs()
254 ## Invalid suffixes: Service Processor Attention
299 * Processor User's Manuals, sections 4.10.4.1 and 5.10.6.1, respectively: in ppc_radix64_is_valid_level()
280 processor.
91 /* Broadcast MCA signal for processor version 06H_EH and above */
219 #define PB_CML_FAULT_PROCESSOR BIT(3) /* Processor Fault Detected */
56 bswap32s(&ehdr->e_flags); /* Processor-specific flags */ in bswap_ehdr()
552 The PCOMMIT instruction was never included in any physical processor.
541 uint64_t vpidr_el2; /* Virtualization Processor ID Register */2547 * Return true if the processor is in secure state.3009 * the same thing as the current security state of the processor!3181 * Rebuild the cached TBFLAGS for arbitrary changed processor state.
2094 * IC IVAU even if the emulated processor does not normally require it. in arm_cpu_realizefn()2318 * Disable the security extension feature bits in the processor in arm_cpu_realizefn()2357 * Disable the hypervisor feature bits in the processor feature in arm_cpu_realizefn()
28 processor in collaboration with the University of California at Berkeley,
395 * determined by the pre-processor instead of the compiler, you'll
494 #define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
1008 * control processor whose boot firmware initializes the INITSVTOR* in armsse_realize()1010 * the control processor, so instead we behave in the way that the in armsse_realize()
74 * the newly stored data. This feature is supported in processor versions