Searched full:processor (Results 126 – 150 of 262) sorted by relevance
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4 #include "qemu/processor.h"
69 * no explicit memory barrier for the processor.
343 * Tries to read the unique processor number from the Kernel Processor Control
679 /* build Processor object for each processor */ in build_cpus_aml()
2051 * 5.2.29.1 Processor hierarchy node structure (Type 0)2060 build_append_byte(tbl, 0); /* Type 0 - processor */ in build_processor_hierarchy_node()2065 build_append_int_noprefix(tbl, id, 4); /* ACPI Processor ID */ in build_processor_hierarchy_node()2146 * 5.2.29 Processor Properties Topology Table (PPTT)2196 (1 << 1) | /* ACPI Processor ID valid */ in build_pptt()2210 (1 << 1) | /* ACPI Processor ID valid */ in build_pptt()2211 (1 << 2) | /* Processor is a Thread */ in build_pptt()
138 /* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */553 /* Virtual processor areas */
370 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */876 /* Intel Processor Trace */917 /* Read Processor ID */1098 /* Processor ignores nested data breakpoints */2054 /* processor features (e.g. for CPUID insn) */2264 * nodes per processor2283 /* Enable auto level-increase for Intel Processor Trace leave */
143 /* Older CPU cannot support a newer processor's compat mode */ in pcc_compat()
1067 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ in powerpc_excp_booke()1870 * wakeup the processor in p9_next_unmasked_interrupt()2147 * processor has_work implementation and the logic in this function. in p7_deliver_interrupt()2221 * processor has_work implementation and the logic in this function. in p8_deliver_interrupt()2305 * processor has_work implementation and the logic in this function. in p9_deliver_interrupt()2423 * processor has_work implementation and the logic in this function. in ppc_deliver_interrupt()
121 * remapped to the Cortex-M3 processor executable region in m2sxxx_soc_realize()
565 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ in build_srat()773 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */ in build_madt()790 /* Processor Power Efficiency Class */ in build_madt()
74 | 0xffffffe0 | 8 | Application processor entry point code |
249 case 0x1f000030: /* Processor version */ in sh7750_mem_readl()255 case 0x1f000044: /* Processor revision */ in sh7750_mem_readl()
212 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", in pnv_dt_core()1063 /* Create the processor chips */ in pnv_init()1103 * per core, so adjust topology here. pnv_dt_core() processor in pnv_init()1425 * Allowed core identifiers on a POWER8 Processor Chip :1544 /* Processor Service Interface (PSI) Host Bridge */ in pnv_chip_power8_realize()1847 /* Processor Service Interface (PSI) Host Bridge */ in pnv_chip_power9_realize()2129 /* Processor Service Interface (PSI) Host Bridge */ in pnv_chip_power10_realize()
44 * "PowerPC Processor binding to IEEE 1275" defines the initial MSR state in spapr_reset_vcpu()
205 # Change processor state
195 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ in cpu_loop()
11 processor(``SPR``).
18 bswaps(&ehdr->e_flags); /* Processor-specific flags */
IBM PPS Model 6015 | WH | k | W |& k K { @ @ @ { ...
432 dc->desc = "SCLP (Service-Call Logical Processor)"; in sclp_class_init()
2 * QEMU model of the IPI Inter Processor Interrupt block
99 /* Maximum number of virtual CPUs in legacy multi-processor guests. */