Searched +full:power +full:- +full:domains (Results 1 – 14 of 14) sorted by relevance
/qemu/docs/tools/ |
H A D | qemu-vmsr-helper.rst | 6 -------- 8 **qemu-vmsr-helper** [*OPTION*] 11 ----------- 15 Accessing the RAPL (Running Average Power Limit) MSR enables the RAPL powercap 16 driver to advertise and monitor the power consumption or accumulated energy 17 consumption of different power domains, such as CPU packages, DRAM, and other 23 :program:`qemu-vmsr-helper` is that external helper; it creates a listener 29 :program:`qemu-vmsr-helper`. 31 After connecting to the socket, :program:`qemu-vmsr-helper` can 35 :program:`qemu-vmsr-helper` can also use the systemd socket activation [all …]
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/qemu/docs/specs/ |
H A D | rapl-msr.rst | 5 The RAPL interface (Running Average Power Limit) is advertising the accumulated 6 energy consumption of various power domains (e.g. CPU packages, DRAM, etc.). 9 MSR_PKG_ENERGY_STATUS for the CPU package power domain. These MSRs are 64 bits 12 Thanks to KVM's `MSR filtering <msr-filter-patch_>`__ functionality, 17 .. _msr-filter-patch: https://patchwork.kernel.org/project/kvm/patch/20200916202951.23760-7-graf@am… 29 spec and specify the power limit of the package, provide range of parameter(min 30 power, max power,..) and also the information of the multiplier for the energy 31 counter to calculate the power. Those MSRs are populated once at the beginning 37 it with the UNIT provided above you'll get the power in micro-joules. This 45 core that belongs to PKG-0 will not be able to get the value of PKG-1 and [all …]
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H A D | ppc-spapr-hotplug.rst | 7 "logical"/para-virtual resources like memory, CPUs, and "physical" 8 host-bridges, which are generally managed by the host/hypervisor and provided 10 are documented extensively in section 13 of the Linux on Power Architecture 14 Dynamic-reconfiguration Connectors 26 the name/index/power-domain/type of each DRC allocated to a guest at 33 for hot plugged resources described under :ref:`guest-host-interface`. 37 of ``ibm,drc-indexes``: 39 ``ibm,drc-names`` 40 ----------------- 42 First 4-bytes: big-endian (BE) encoded integer denoting the number of entries. [all …]
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/qemu/include/hw/xen/interface/ |
H A D | grant_table.h | 1 /* SPDX-License-Identifier: MIT */ 6 * page-ownership transfers. 20 * between domains. This shared memory interface underpins the split 25 * permissions other domains have on its pages. Entries in the grant 31 * This capability-based system allows shared-memory communications 32 * between unprivileged domains. A grant reference also encapsulates 35 * it possible to share memory correctly with domains running in 43 /* Some rough guidelines on accessing and updating grant-table entries 44 * in a concurrency-safe manner. For more information, Linux contains a 46 …* http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/xen/grant-table.c;… [all …]
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H A D | trace.h | 1 /* SPDX-License-Identifier: MIT */ 24 #define TRC_HW 0x0080f000 /* Xen hardware-related traces */ 25 #define TRC_GUEST 0x0800f000 /* Guest-generated traces */ 41 #define TRC_SCHED_CLASS 0x00022000 /* Scheduler-specific */ 54 #define TRC_SCHED_ID_SHIFT (TRC_SUBCLS_SHIFT - TRC_SCHED_ID_BITS) 55 #define TRC_SCHED_ID_MASK (((1UL<<TRC_SCHED_ID_BITS) - 1) << TRC_SCHED_ID_SHIFT) 58 /* Per-scheduler IDs, to identify scheduler specific events */ 66 /* Per-scheduler tracing */ 73 #define TRC_DOM0_DOMOPS 0x00041000 /* Domains manipulations */ 76 #define TRC_HW_PM 0x00801000 /* Power management traces */ [all …]
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/qemu/hw/ppc/ |
H A D | spapr_drc.c | 10 * See the COPYING file in the top-level directory. 20 #include "qapi/qapi-events-qdev.h" 22 #include "qemu/error-report.h" 24 #include "hw/pci-host/spapr.h" /* spapr_phb_remove_pci_device_cb callback */ 30 #define DRC_CONTAINER_PATH "dr-connector" 32 #define DRC_INDEX_ID_MASK ((1ULL << DRC_INDEX_TYPE_SHIFT) - 1) 38 return 1 << drck->typeshift; in spapr_drc_type() 46 * unique. this is how we encode the DRC type on bare-metal in spapr_drc_index() 49 return (drck->typeshift << DRC_INDEX_TYPE_SHIFT) in spapr_drc_index() 50 | (drc->id & DRC_INDEX_ID_MASK); in spapr_drc_index() [all …]
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/qemu/docs/ |
H A D | pcie.txt | 25 QEMU does not have a clear socket-device matching mechanism 43 Note: Integrated Endpoints are not hot-pluggable. 51 (2) PCI Express Root Ports (pcie-root-port), for starting exclusively 54 (3) PCI Express to PCI Bridge (pcie-pci-bridge), for starting legacy PCI 57 (4) Extra Root Complexes (pxb-pcie), if multiple PCI Express Root Buses 61 ---------------------------------------------------------------------------- 63 ----------- ------------------ ------------------- -------------- 64 | PCI Dev | | PCIe Root Port | | PCIe-PCI Bridge | | pxb-pcie | 65 ----------- ------------------ ------------------- -------------- 68 -device <dev>[,bus=pcie.0] [all …]
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/qemu/target/xtensa/core-test_kc705_be/ |
H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 10 Copyright (c) 1999-2015 Tensilica Inc. 44 /*---------------------------------------------------------------------- 46 ----------------------------------------------------------------------*/ 48 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */ 54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ 88 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ [all …]
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/qemu/target/xtensa/core-de212/ |
H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 10 Copyright (c) 1999-2015 Tensilica Inc. 44 /*---------------------------------------------------------------------- 46 ----------------------------------------------------------------------*/ 48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ 89 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ [all …]
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/qemu/target/xtensa/core-sample_controller/ |
H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 10 Copyright (c) 1999-2016 Tensilica Inc. 44 /*---------------------------------------------------------------------- 46 ----------------------------------------------------------------------*/ 48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 55 #define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */ 56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ 89 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ [all …]
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/qemu/target/xtensa/core-test_mmuhifi_c3/ |
H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 10 Copyright (c) 1999-2019 Tensilica Inc. 45 /*---------------------------------------------------------------------- 47 ----------------------------------------------------------------------*/ 49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 57 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ 88 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ [all …]
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/qemu/target/xtensa/core-de233_fpu/ |
H A D | core-isa.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 10 Copyright (c) 1999-2020 Tensilica Inc. 34 //depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko) 46 /*---------------------------------------------------------------------- 48 ----------------------------------------------------------------------*/ 50 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 56 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 57 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 58 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 69 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ [all …]
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/qemu/include/hw/ppc/ |
H A D | spapr.h | 8 #include "hw/mem/pc-dimm.h" 32 #define TYPE_SPAPR_RTC "spapr-rtc" 44 #define TYPE_SPAPR_MACHINE "spapr-machine" 72 /* Nested KVM-HV */ 104 /* SPAPR_CAP_IBS (cap-ibs) */ 117 * kernel source. It represents the amount of associativity domains 118 * for non-CPU resources. 121 * array for any non-CPU resource. 146 bool dr_phb_enabled; /* enable dynamic-reconfig/hotplug of PHBs */ 151 bool pre_4_1_migration; /* don't migrate hpt-max-page-size */ [all …]
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/qemu/hw/pci/ |
H A D | pci.c | 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-properties-system.h" 35 #include "migration/qemu-file-types.h" 42 #include "qemu/error-report.h" 52 #include "pci-internal.h" 78 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1), 81 DEFINE_PROP_INT32("rombar", PCIDevice, rom_bar, -1), 84 DEFINE_PROP_BIT("x-pcie-lnksta-dllla", PCIDevice, cap_present, 86 DEFINE_PROP_BIT("x-pcie-extcap-init", PCIDevice, cap_present, 90 DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), [all …]
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