Lines Matching +full:power +full:- +full:domains
2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2015 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
89 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
90 #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
100 #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
101 #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
103 #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
106 #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
118 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
119 #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
120 #define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */
154 #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
165 /*----------------------------------------------------------------------
167 ----------------------------------------------------------------------*/
171 #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
173 #define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
174 (1 = 5-stage, 2 = 7-stage) */
189 #define XCHAL_BUILD_UNIQUE_ID 0x0005A9EB /* 22-bit sw build ID */
213 /*----------------------------------------------------------------------
215 ----------------------------------------------------------------------*/
217 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
218 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
222 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */
223 #define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */
243 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
249 /*----------------------------------------------------------------------
251 ----------------------------------------------------------------------*/
284 /*----------------------------------------------------------------------
286 ----------------------------------------------------------------------*/
323 /*----------------------------------------------------------------------
325 ----------------------------------------------------------------------*/
328 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
329 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
428 #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
443 * configured as external (level-triggered, edge-triggered, or NMI).
485 /*----------------------------------------------------------------------
487 ----------------------------------------------------------------------*/
555 /*----------------------------------------------------------------------
557 ----------------------------------------------------------------------*/
564 /* On-Chip Debug (OCD) */
582 /*----------------------------------------------------------------------
584 ----------------------------------------------------------------------*/
586 /* See core-matmap.h header file for more details. */
597 usable for an MMU-based OS */
605 /*----------------------------------------------------------------------
607 ----------------------------------------------------------------------*/