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/qemu/hw/microblaze/
H A Dxlnx-zynqmp-pmu.c2 * Xilinx Zynq MPSoC PMU (Power Management Unit) emulation
26 #include "hw/intc/xlnx-pmu-iomod-intc.h"
29 /* Define the PMU device */
31 #define TYPE_XLNX_ZYNQMP_PMU_SOC "xlnx-zynqmp-pmu-soc"
64 object_initialize_child(obj, "pmu-cpu", &s->cpu, TYPE_MICROBLAZE_CPU); in xlnx_zynqmp_pmu_soc_init()
128 /* xlnx-zynqmp-pmu-soc causes crashes when cold-plugged twice */ in xlnx_zynqmp_pmu_soc_class_init()
148 /* Define the PMU Machine */ in type_init()
152 XlnxZynqMPPMUSoCState *pmu = g_new0(XlnxZynqMPPMUSoCState, 1); in type_init() local
158 memory_region_init_rom(pmu_rom, NULL, "xlnx-zynqmp-pmu.rom", in type_init()
164 memory_region_init_ram(pmu_ram, NULL, "xlnx-zynqmp-pmu.ram", in type_init()
[all …]
H A Dmeson.build5 microblaze_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-zynqmp-pmu.c'))
/qemu/include/hw/misc/macio/
H A Dpmu.h2 * Definitions for talking to the PMU. The PMU is a microcontroller
19 * PMU commands
36 #define PMU_SET_INTR_MASK 0x70 /* set PMU interrupt mask */
41 #define PMU_POWER_EVENTS 0x8f /* Send power-event commands to PMU */
46 #define PMU_SYSTEM_READY 0xdf /* tell PMU we are awake */
48 #define PMU_READ_PMU_RAM 0xe8 /* read the PMU RAM... ??? */
49 #define PMU_GET_VERSION 0xea /* read the PMU version */
66 /* Bits in PMU interrupt and interrupt mask bytes */
74 /* Other bits in PMU interrupt valid when PMU_INT_ADB is set */
96 /* Kind of PMU (model) */
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H A Dmacio.h35 #include "hw/misc/macio/pmu.h"
112 PMUState pmu; member
/qemu/hw/misc/macio/
H A Dpmu.c2 * QEMU PowerMac PMU device support
35 #include "hw/misc/macio/pmu.h"
50 /* PMU returns time_t's offset from Jan 1, 1904, not 1970 */
111 "PMU: INT_ACK command, invalid len: %d want: 0\n", in pmu_cmd_int_ack()
143 "PMU: SET_INT_MASK command, invalid len: %d want: 1\n", in pmu_cmd_set_int_mask()
177 "PMU: ADB PACKET, invalid len: %d want at least 2\n", in pmu_cmd_adb()
195 "PMU: ADB Autopoll requires 4 bytes, got %d\n", in pmu_cmd_adb()
213 "PMU: ADB len is %d > %d (in_len -3)...erroring\n", in pmu_cmd_adb()
217 qemu_log_mask(LOG_GUEST_ERROR, "PMU: ADB command too big!\n"); in pmu_cmd_adb()
251 "PMU: ADB POLL OFF command, invalid len: %d want: 0\n", in pmu_cmd_adb_poll_off()
[all …]
H A Dtrace-events24 # pmu.c
26 pmu_one_sec_timer(void) "PMU one sec..."
27 pmu_cmd_set_int_mask(int intmask) "Setting PMU int mask to 0x%02x"
33 pmu_dispatch_unknown_cmd(int cmd) "Unknown PMU command 0x%02x"
H A Dmacio.c319 /* PMU */ in macio_newworld_realize()
320 object_initialize_child(OBJECT(s), "pmu", &s->pmu, TYPE_VIA_PMU); in macio_newworld_realize()
321 object_property_set_link(OBJECT(&s->pmu), "gpio", OBJECT(sbd), in macio_newworld_realize()
323 qdev_prop_set_bit(DEVICE(&s->pmu), "has-adb", ns->has_adb); in macio_newworld_realize()
324 if (!qdev_realize(DEVICE(&s->pmu), BUS(&s->macio_bus), errp)) { in macio_newworld_realize()
327 sbd = SYS_BUS_DEVICE(&s->pmu); in macio_newworld_realize()
409 DEFINE_PROP_BOOL("has-pmu", NewWorldMacIOState, has_pmu, false),
H A Dmeson.build6 macio_ss.add(when: 'CONFIG_MAC_PMU', if_true: files('pmu.c'))
/qemu/hw/misc/
H A Dimx7_ccm.c4 * i.MX7 CCM, PMU and ANALOG IP blocks emulation code
27 memset(s->pmu, 0, sizeof(s->pmu)); in imx7_analog_reset()
189 memory_region_init_io(&s->mmio.pmu, in imx7_analog_init()
192 s->pmu, in imx7_analog_init()
193 TYPE_IMX7_ANALOG ".pmu", in imx7_analog_init()
194 sizeof(s->pmu)); in imx7_analog_init()
197 0x200, &s->mmio.pmu); in imx7_analog_init()
291 VMSTATE_UINT32_ARRAY(pmu, IMX7AnalogState, PMU_MAX),
H A Dexynos4210_pmu.c2 * Exynos4210 Power Management Unit (PMU) Emulation
22 * This model implements PMU registers just as a bulk of memory. Currently,
24 * uses PMU INFORM5 register as a holding pen.
63 * Offsets for PMU registers
94 #define PMU_DEBUG 0x0A00 /* PMU debug register */
397 #define TYPE_EXYNOS4210_PMU "exynos4210.pmu"
409 PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n"); in exynos4210_pmu_poweroff()
428 PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset); in exynos4210_pmu_read()
455 PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset); in exynos4210_pmu_write()
487 "exynos4210.pmu", EXYNOS4210_PMU_REGS_MEM_SIZE); in exynos4210_pmu_init()
[all …]
/qemu/docs/system/arm/
H A Dcpu-features.rst9 is the Performance Monitoring Unit (PMU). CPU types such as the
13 a PMU, then the ``-cpu`` parameter should contain ``pmu=off`` on the QEMU
14 command line, i.e. ``-cpu cortex-a15,pmu=off``.
47 "sve1664": true, "pmu": true, "sve1792": true, "sve1920": true,
54 We see that the ``max`` CPU type has the ``pmu``, ``aarch64``, ``sve``, and many
62 (2) Let's try to disable the PMU::
64 (QEMU) query-cpu-model-expansion type=full model={"name":"max","props":{"pmu":false}}
67 "sve1664": true, "pmu": false, "sve1792": true, "sve1920": true,
74 We see it worked, as ``pmu`` is now ``false``.
93 "sve1664": false, "pmu": true, "sve1792": false, "sve1920": false,
[all …]
H A Demulation.rst112 - FEAT_PMUv3 (PMU extension version 3)
113 - FEAT_PMUv3p1 (PMU Extensions v3.1)
114 - FEAT_PMUv3p4 (PMU Extensions v3.4)
115 - FEAT_PMUv3p5 (PMU Extensions v3.5)
/qemu/include/hw/misc/
H A Dimx7_ccm.h4 * i.MX7 CCM, PMU and ANALOG IP blocks emulation code
133 MemoryRegion pmu; member
137 uint32_t pmu[PMU_MAX]; member
H A Dxlnx-zynqmp-apu-ctrl.h79 /* WFIs towards PMU. */
/qemu/tests/qtest/
H A Darm-cpu-features.c462 assert_has_feature_enabled(qts, "cortex-a15", "pmu"); in test_query_cpu_model_expansion()
465 /* Enabling and disabling pmu should always work. */ in test_query_cpu_model_expansion()
466 assert_has_feature_enabled(qts, "max", "pmu"); in test_query_cpu_model_expansion()
467 assert_set_feature(qts, "max", "pmu", false); in test_query_cpu_model_expansion()
468 assert_set_feature(qts, "max", "pmu", true); in test_query_cpu_model_expansion()
477 assert_has_feature_enabled(qts, "cortex-a57", "pmu"); in test_query_cpu_model_expansion()
480 assert_has_feature_enabled(qts, "a64fx", "pmu"); in test_query_cpu_model_expansion()
557 kvm_supports_pmu = resp_get_feature(resp, "pmu"); in test_query_cpu_model_expansion_kvm()
564 /* If we have pmu then we should be able to toggle it. */ in test_query_cpu_model_expansion_kvm()
565 assert_set_feature(qts, "host", "pmu", false); in test_query_cpu_model_expansion_kvm()
[all …]
/qemu/hw/ppc/
H A Dmac_newworld.c361 qdev_prop_set_bit(dev, "has-pmu", has_pmu); in ppc_core99_init()
412 dev = DEVICE(object_resolve_path_component(macio, "pmu")); in ppc_core99_init()
600 return g_strdup("pmu"); in core99_get_via_config()
603 return g_strdup("pmu-adb"); in core99_get_via_config()
613 } else if (!strcmp(value, "pmu")) { in core99_set_via_config()
615 } else if (!strcmp(value, "pmu-adb")) { in core99_set_via_config()
619 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n"); in core99_set_via_config()
633 "Valid values are cuda, pmu and pmu-adb"); in core99_instance_init()
/qemu/target/riscv/
H A Dpmu.c2 * RISC-V PMU file.
24 #include "pmu.h"
34 * to provide the correct value as well. Heterogeneous PMU per hart is not
586 error_setg(errp, "\"pmu-mask\" contains invalid bits (0-2) set"); in riscv_pmu_init()
597 error_setg(errp, "Unable to allocate PMU event hash table"); in riscv_pmu_init()
H A Dmeson.build35 'pmu.c',
H A Dpmu.h2 * RISC-V PMU header file.
/qemu/target/loongarch/kvm/
H A Dkvm.c1013 if (cpu->pmu == ON_OFF_AUTO_ON) { in kvm_cpu_check_pmu()
1015 error_setg(errp, "'pmu' feature not supported by KVM on the host"); in kvm_cpu_check_pmu()
1018 } else if (cpu->pmu != ON_OFF_AUTO_AUTO) { in kvm_cpu_check_pmu()
1019 /* disable pmu if ON_OFF_AUTO_OFF is set */ in kvm_cpu_check_pmu()
1143 return LOONGARCH_CPU(obj)->pmu != ON_OFF_AUTO_OFF; in loongarch_get_pmu()
1150 cpu->pmu = value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; in loongarch_set_pmu()
1185 cpu->pmu = ON_OFF_AUTO_AUTO; in kvm_loongarch_cpu_post_init()
1186 object_property_add_bool(OBJECT(cpu), "pmu", loongarch_get_pmu, in kvm_loongarch_cpu_post_init()
1188 object_property_set_description(OBJECT(cpu), "pmu", in kvm_loongarch_cpu_post_init()
/qemu/target/ppc/
H A Dpower8-pmu.h2 * PMU emulation helpers for TCG IBM POWER chips
H A Dmeson.build20 'power8-pmu.c',
H A Dpower8-pmu.c2 * PMU emulation helpers for TCG IBM POWER chips
20 #include "power8-pmu.h"
/qemu/hw/arm/
H A Dbcm2838.c174 /* PMU interrupt */ in bcm2838_realize()
175 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, in bcm2838_realize()
/qemu/target/loongarch/
H A Dloongarch-qmp-cmds.c43 "lsx", "lasx", "lbt", "pmu", "kvm-pv-ipi", "kvm-steal-time", NULL

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